Unified Coverage Report :: Module :: prim_generic_ram_1r1w

Module : prim_generic_ram_1r1w

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1r1w

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	611167672	3492055	0	0
gen_wmask[1].MaskCheckPortA_A	611167672	3492055	0	0
gen_wmask[2].MaskCheckPortA_A	611167672	3492055	0	0
gen_wmask[3].MaskCheckPortA_A	611167672	3492055	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611167672	3492055	0	0
T2	152191	2665	0	0
T3	2772	832	0	0
T4	46944	0	0	0
T5	66465	832	0	0
T6	694580	4774	0	0
T7	380238	3954	0	0
T8	15760	126	0	0
T9	18583	832	0	0
T10	1005634	832	0	0
T11	1197905	14893	0	0
T12	138118	6135	0	0
T15	0	5277	0	0
T17	0	2292	0	0
T23	0	92	0	0
T24	0	105	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611167672	3492055	0	0
T2	152191	2665	0	0
T3	2772	832	0	0
T4	46944	0	0	0
T5	66465	832	0	0
T6	694580	4774	0	0
T7	380238	3954	0	0
T8	15760	126	0	0
T9	18583	832	0	0
T10	1005634	832	0	0
T11	1197905	14893	0	0
T12	138118	6135	0	0
T15	0	5277	0	0
T17	0	2292	0	0
T23	0	92	0	0
T24	0	105	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611167672	3492055	0	0
T2	152191	2665	0	0
T3	2772	832	0	0
T4	46944	0	0	0
T5	66465	832	0	0
T6	694580	4774	0	0
T7	380238	3954	0	0
T8	15760	126	0	0
T9	18583	832	0	0
T10	1005634	832	0	0
T11	1197905	14893	0	0
T12	138118	6135	0	0
T15	0	5277	0	0
T17	0	2292	0	0
T23	0	92	0	0
T24	0	105	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611167672	3492055	0	0
T2	152191	2665	0	0
T3	2772	832	0	0
T4	46944	0	0	0
T5	66465	832	0	0
T6	694580	4774	0	0
T7	380238	3954	0	0
T8	15760	126	0	0
T9	18583	832	0	0
T10	1005634	832	0	0
T11	1197905	14893	0	0
T12	138118	6135	0	0
T15	0	5277	0	0
T17	0	2292	0	0
T23	0	92	0	0
T24	0	105	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			==> MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T6
0	Covered	T2,T4,T5

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	457483007	2139584	0	0
gen_wmask[1].MaskCheckPortA_A	457483007	2139584	0	0
gen_wmask[2].MaskCheckPortA_A	457483007	2139584	0	0
gen_wmask[3].MaskCheckPortA_A	457483007	2139584	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457483007	2139584	0	0
T2	56571	2496	0	0
T3	2772	832	0	0
T4	17622	0	0	0
T5	30048	832	0	0
T6	610200	1664	0	0
T7	217987	1034	0	0
T8	14144	13	0	0
T9	14471	832	0	0
T10	862434	832	0	0
T11	637702	10816	0	0
T12	0	1843	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457483007	2139584	0	0
T2	56571	2496	0	0
T3	2772	832	0	0
T4	17622	0	0	0
T5	30048	832	0	0
T6	610200	1664	0	0
T7	217987	1034	0	0
T8	14144	13	0	0
T9	14471	832	0	0
T10	862434	832	0	0
T11	637702	10816	0	0
T12	0	1843	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457483007	2139584	0	0
T2	56571	2496	0	0
T3	2772	832	0	0
T4	17622	0	0	0
T5	30048	832	0	0
T6	610200	1664	0	0
T7	217987	1034	0	0
T8	14144	13	0	0
T9	14471	832	0	0
T10	862434	832	0	0
T11	637702	10816	0	0
T12	0	1843	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457483007	2139584	0	0
T2	56571	2496	0	0
T3	2772	832	0	0
T4	17622	0	0	0
T5	30048	832	0	0
T6	610200	1664	0	0
T7	217987	1034	0	0
T8	14144	13	0	0
T9	14471	832	0	0
T10	862434	832	0	0
T11	637702	10816	0	0
T12	0	1843	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T7
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	153684665	1352471	0	0
gen_wmask[1].MaskCheckPortA_A	153684665	1352471	0	0
gen_wmask[2].MaskCheckPortA_A	153684665	1352471	0	0
gen_wmask[3].MaskCheckPortA_A	153684665	1352471	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153684665	1352471	0	0
T2	95620	169	0	0
T4	29322	0	0	0
T5	36417	0	0	0
T6	84380	3110	0	0
T7	162251	2920	0	0
T8	1616	113	0	0
T9	4112	0	0	0
T10	143200	0	0	0
T11	560203	4077	0	0
T12	138118	4292	0	0
T15	0	5277	0	0
T17	0	2292	0	0
T23	0	92	0	0
T24	0	105	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153684665	1352471	0	0
T2	95620	169	0	0
T4	29322	0	0	0
T5	36417	0	0	0
T6	84380	3110	0	0
T7	162251	2920	0	0
T8	1616	113	0	0
T9	4112	0	0	0
T10	143200	0	0	0
T11	560203	4077	0	0
T12	138118	4292	0	0
T15	0	5277	0	0
T17	0	2292	0	0
T23	0	92	0	0
T24	0	105	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153684665	1352471	0	0
T2	95620	169	0	0
T4	29322	0	0	0
T5	36417	0	0	0
T6	84380	3110	0	0
T7	162251	2920	0	0
T8	1616	113	0	0
T9	4112	0	0	0
T10	143200	0	0	0
T11	560203	4077	0	0
T12	138118	4292	0	0
T15	0	5277	0	0
T17	0	2292	0	0
T23	0	92	0	0
T24	0	105	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153684665	1352471	0	0
T2	95620	169	0	0
T4	29322	0	0	0
T5	36417	0	0	0
T6	84380	3110	0	0
T7	162251	2920	0	0
T8	1616	113	0	0
T9	4112	0	0	0
T10	143200	0	0	0
T11	560203	4077	0	0
T12	138118	4292	0	0
T15	0	5277	0	0
T17	0	2292	0	0
T23	0	92	0	0
T24	0	105	0	0