Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	460028901	2953639	0	0
DepthKnown_A	460028901	459898133	0	0
RvalidKnown_A	460028901	459898133	0	0
WreadyKnown_A	460028901	459898133	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460028901	2953639	0	0
T2	56571	3327	0	0
T3	2772	1663	0	0
T4	17622	0	0	0
T5	30048	832	0	0
T6	610200	2495	0	0
T7	217987	0	0	0
T8	14144	0	0	0
T9	14471	832	0	0
T10	862434	832	0	0
T11	637702	18324	0	0
T13	0	1663	0	0
T14	0	1663	0	0
T15	0	4990	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460028901	459898133	0	0
T1	5752	5536	0	0
T2	56571	56473	0	0
T3	2772	2716	0	0
T4	17622	17562	0	0
T5	30048	29973	0	0
T6	610200	610119	0	0
T7	217987	217916	0	0
T8	14144	14092	0	0
T9	14471	14411	0	0
T10	862434	862340	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460028901	459898133	0	0
T1	5752	5536	0	0
T2	56571	56473	0	0
T3	2772	2716	0	0
T4	17622	17562	0	0
T5	30048	29973	0	0
T6	610200	610119	0	0
T7	217987	217916	0	0
T8	14144	14092	0	0
T9	14471	14411	0	0
T10	862434	862340	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460028901	459898133	0	0
T1	5752	5536	0	0
T2	56571	56473	0	0
T3	2772	2716	0	0
T4	17622	17562	0	0
T5	30048	29973	0	0
T6	610200	610119	0	0
T7	217987	217916	0	0
T8	14144	14092	0	0
T9	14471	14411	0	0
T10	862434	862340	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	460028901	3133865	0	0
DepthKnown_A	460028901	459898133	0	0
RvalidKnown_A	460028901	459898133	0	0
WreadyKnown_A	460028901	459898133	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460028901	3133865	0	0
T2	56571	2496	0	0
T3	2772	832	0	0
T4	17622	0	0	0
T5	30048	3723	0	0
T6	610200	4533	0	0
T7	217987	0	0	0
T8	14144	0	0	0
T9	14471	3721	0	0
T10	862434	832	0	0
T11	637702	22343	0	0
T13	0	832	0	0
T14	0	832	0	0
T15	0	3328	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460028901	459898133	0	0
T1	5752	5536	0	0
T2	56571	56473	0	0
T3	2772	2716	0	0
T4	17622	17562	0	0
T5	30048	29973	0	0
T6	610200	610119	0	0
T7	217987	217916	0	0
T8	14144	14092	0	0
T9	14471	14411	0	0
T10	862434	862340	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460028901	459898133	0	0
T1	5752	5536	0	0
T2	56571	56473	0	0
T3	2772	2716	0	0
T4	17622	17562	0	0
T5	30048	29973	0	0
T6	610200	610119	0	0
T7	217987	217916	0	0
T8	14144	14092	0	0
T9	14471	14411	0	0
T10	862434	862340	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460028901	459898133	0	0
T1	5752	5536	0	0
T2	56571	56473	0	0
T3	2772	2716	0	0
T4	17622	17562	0	0
T5	30048	29973	0	0
T6	610200	610119	0	0
T7	217987	217916	0	0
T8	14144	14092	0	0
T9	14471	14411	0	0
T10	862434	862340	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	460028901	196124	0	0
DepthKnown_A	460028901	459898133	0	0
RvalidKnown_A	460028901	459898133	0	0
WreadyKnown_A	460028901	459898133	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460028901	196124	0	0
T2	56571	38	0	0
T3	2772	0	0	0
T4	17622	0	0	0
T5	30048	0	0	0
T6	610200	192	0	0
T7	217987	765	0	0
T8	14144	29	0	0
T9	14471	0	0	0
T10	862434	0	0	0
T11	637702	472	0	0
T12	0	1105	0	0
T15	0	730	0	0
T17	0	585	0	0
T23	0	24	0	0
T24	0	27	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460028901	459898133	0	0
T1	5752	5536	0	0
T2	56571	56473	0	0
T3	2772	2716	0	0
T4	17622	17562	0	0
T5	30048	29973	0	0
T6	610200	610119	0	0
T7	217987	217916	0	0
T8	14144	14092	0	0
T9	14471	14411	0	0
T10	862434	862340	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460028901	459898133	0	0
T1	5752	5536	0	0
T2	56571	56473	0	0
T3	2772	2716	0	0
T4	17622	17562	0	0
T5	30048	29973	0	0
T6	610200	610119	0	0
T7	217987	217916	0	0
T8	14144	14092	0	0
T9	14471	14411	0	0
T10	862434	862340	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460028901	459898133	0	0
T1	5752	5536	0	0
T2	56571	56473	0	0
T3	2772	2716	0	0
T4	17622	17562	0	0
T5	30048	29973	0	0
T6	610200	610119	0	0
T7	217987	217916	0	0
T8	14144	14092	0	0
T9	14471	14411	0	0
T10	862434	862340	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	460028901	441542	0	0
DepthKnown_A	460028901	459898133	0	0
RvalidKnown_A	460028901	459898133	0	0
WreadyKnown_A	460028901	459898133	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460028901	441542	0	0
T2	56571	38	0	0
T3	2772	0	0	0
T4	17622	0	0	0
T5	30048	0	0	0
T6	610200	896	0	0
T7	217987	765	0	0
T8	14144	29	0	0
T9	14471	0	0	0
T10	862434	0	0	0
T11	637702	2152	0	0
T12	0	5010	0	0
T15	0	728	0	0
T17	0	1341	0	0
T23	0	24	0	0
T24	0	93	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460028901	459898133	0	0
T1	5752	5536	0	0
T2	56571	56473	0	0
T3	2772	2716	0	0
T4	17622	17562	0	0
T5	30048	29973	0	0
T6	610200	610119	0	0
T7	217987	217916	0	0
T8	14144	14092	0	0
T9	14471	14411	0	0
T10	862434	862340	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460028901	459898133	0	0
T1	5752	5536	0	0
T2	56571	56473	0	0
T3	2772	2716	0	0
T4	17622	17562	0	0
T5	30048	29973	0	0
T6	610200	610119	0	0
T7	217987	217916	0	0
T8	14144	14092	0	0
T9	14471	14411	0	0
T10	862434	862340	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460028901	459898133	0	0
T1	5752	5536	0	0
T2	56571	56473	0	0
T3	2772	2716	0	0
T4	17622	17562	0	0
T5	30048	29973	0	0
T6	610200	610119	0	0
T7	217987	217916	0	0
T8	14144	14092	0	0
T9	14471	14411	0	0
T10	862434	862340	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	460028901	6782978	0	0
DepthKnown_A	460028901	459898133	0	0
RvalidKnown_A	460028901	459898133	0	0
WreadyKnown_A	460028901	459898133	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460028901	6782978	0	0
T1	5752	210	0	0
T2	56571	302	0	0
T3	2772	46	0	0
T4	17622	107	0	0
T5	30048	838	0	0
T6	610200	1034	0	0
T7	217987	6205	0	0
T8	14144	1382	0	0
T9	14471	73	0	0
T10	862434	48960	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460028901	459898133	0	0
T1	5752	5536	0	0
T2	56571	56473	0	0
T3	2772	2716	0	0
T4	17622	17562	0	0
T5	30048	29973	0	0
T6	610200	610119	0	0
T7	217987	217916	0	0
T8	14144	14092	0	0
T9	14471	14411	0	0
T10	862434	862340	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460028901	459898133	0	0
T1	5752	5536	0	0
T2	56571	56473	0	0
T3	2772	2716	0	0
T4	17622	17562	0	0
T5	30048	29973	0	0
T6	610200	610119	0	0
T7	217987	217916	0	0
T8	14144	14092	0	0
T9	14471	14411	0	0
T10	862434	862340	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460028901	459898133	0	0
T1	5752	5536	0	0
T2	56571	56473	0	0
T3	2772	2716	0	0
T4	17622	17562	0	0
T5	30048	29973	0	0
T6	610200	610119	0	0
T7	217987	217916	0	0
T8	14144	14092	0	0
T9	14471	14411	0	0
T10	862434	862340	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	460028901	13575116	0	0
DepthKnown_A	460028901	459898133	0	0
RvalidKnown_A	460028901	459898133	0	0
WreadyKnown_A	460028901	459898133	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460028901	13575116	0	0
T1	5752	210	0	0
T2	56571	302	0	0
T3	2772	46	0	0
T4	17622	107	0	0
T5	30048	3655	0	0
T6	610200	4305	0	0
T7	217987	6149	0	0
T8	14144	1382	0	0
T9	14471	355	0	0
T10	862434	48960	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460028901	459898133	0	0
T1	5752	5536	0	0
T2	56571	56473	0	0
T3	2772	2716	0	0
T4	17622	17562	0	0
T5	30048	29973	0	0
T6	610200	610119	0	0
T7	217987	217916	0	0
T8	14144	14092	0	0
T9	14471	14411	0	0
T10	862434	862340	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460028901	459898133	0	0
T1	5752	5536	0	0
T2	56571	56473	0	0
T3	2772	2716	0	0
T4	17622	17562	0	0
T5	30048	29973	0	0
T6	610200	610119	0	0
T7	217987	217916	0	0
T8	14144	14092	0	0
T9	14471	14411	0	0
T10	862434	862340	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460028901	459898133	0	0
T1	5752	5536	0	0
T2	56571	56473	0	0
T3	2772	2716	0	0
T4	17622	17562	0	0
T5	30048	29973	0	0
T6	610200	610119	0	0
T7	217987	217916	0	0
T8	14144	14092	0	0
T9	14471	14411	0	0
T10	862434	862340	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0