Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T12
1	0	Covered	T7,T8,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T8
1	0	Unreachable
1	1	Covered	T7,T8,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T11

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T6,T11
1	0	Covered	T2,T6,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Unreachable
1	1	Covered	T2,T6,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T6,T7
1	0	Covered	T2,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	764852337	609673727	0	0
CheckNGreaterZero_A	2868	2868	0	0
GntImpliesReady_A	764852337	3901551	0	0
GntImpliesValid_A	764852337	3901551	0	0
GrantKnown_A	764852337	609673727	0	0
IdxKnown_A	764852337	609673727	0	0
IndexIsCorrect_A	764852337	3901551	0	0
LockArbDecision_A	764852337	0	0	0
NoReadyValidNoGrant_A	764852337	0	0	0
ReadyAndValidImplyGrant_A	764852337	3901551	0	0
ReqAndReadyImplyGrant_A	764852337	3901551	0	0
ReqImpliesValid_A	764852337	3901551	0	0
ReqStaysHighUntilGranted0_M	764852337	0	0	0
RoundRobin_A	764852337	6	0	956
ValidKnown_A	764852337	609673727	0	0
gen_data_port_assertion.DataFlow_A	764852337	3901551	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764852337	609673727	0	0
T1	5752	5536	0	0
T2	152191	151238	0	0
T3	2772	2716	0	0
T4	76266	46114	0	0
T5	102882	66241	0	0
T6	778960	694098	0	0
T7	542489	374484	0	0
T8	17376	15708	0	0
T9	22695	18523	0	0
T10	1148834	1005540	0	0
T11	1120406	555558	0	0
T12	276236	132232	0	0
T13	66432	66432	0	0
T14	0	122256	0	0
T15	0	601680	0	0
T16	0	48080	0	0
T17	0	51960	0	0
T23	0	3680	0	0
T24	0	3408	0	0
T25	0	1344	0	0
T26	0	712	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2868	2868	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764852337	3901551	0	0
T2	152191	2717	0	0
T3	2772	832	0	0
T4	46944	0	0	0
T5	66465	832	0	0
T6	694580	4973	0	0
T7	542489	5858	0	0
T8	17376	169	0	0
T9	22695	832	0	0
T10	1148834	832	0	0
T11	1758108	15394	0	0
T12	276236	9274	0	0
T13	66432	0	0	0
T14	122871	0	0	0
T15	606620	6373	0	0
T17	0	2933	0	0
T23	4088	152	0	0
T24	0	128	0	0
T25	0	117	0	0
T26	0	14	0	0
T30	0	9086	0	0
T37	0	9841	0	0
T43	0	527	0	0
T44	0	613	0	0
T45	0	6	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764852337	3901551	0	0
T2	152191	2717	0	0
T3	2772	832	0	0
T4	46944	0	0	0
T5	66465	832	0	0
T6	694580	4973	0	0
T7	542489	5858	0	0
T8	17376	169	0	0
T9	22695	832	0	0
T10	1148834	832	0	0
T11	1758108	15394	0	0
T12	276236	9274	0	0
T13	66432	0	0	0
T14	122871	0	0	0
T15	606620	6373	0	0
T17	0	2933	0	0
T23	4088	152	0	0
T24	0	128	0	0
T25	0	117	0	0
T26	0	14	0	0
T30	0	9086	0	0
T37	0	9841	0	0
T43	0	527	0	0
T44	0	613	0	0
T45	0	6	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764852337	609673727	0	0
T1	5752	5536	0	0
T2	152191	151238	0	0
T3	2772	2716	0	0
T4	76266	46114	0	0
T5	102882	66241	0	0
T6	778960	694098	0	0
T7	542489	374484	0	0
T8	17376	15708	0	0
T9	22695	18523	0	0
T10	1148834	1005540	0	0
T11	1120406	555558	0	0
T12	276236	132232	0	0
T13	66432	66432	0	0
T14	0	122256	0	0
T15	0	601680	0	0
T16	0	48080	0	0
T17	0	51960	0	0
T23	0	3680	0	0
T24	0	3408	0	0
T25	0	1344	0	0
T26	0	712	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764852337	609673727	0	0
T1	5752	5536	0	0
T2	152191	151238	0	0
T3	2772	2716	0	0
T4	76266	46114	0	0
T5	102882	66241	0	0
T6	778960	694098	0	0
T7	542489	374484	0	0
T8	17376	15708	0	0
T9	22695	18523	0	0
T10	1148834	1005540	0	0
T11	1120406	555558	0	0
T12	276236	132232	0	0
T13	66432	66432	0	0
T14	0	122256	0	0
T15	0	601680	0	0
T16	0	48080	0	0
T17	0	51960	0	0
T23	0	3680	0	0
T24	0	3408	0	0
T25	0	1344	0	0
T26	0	712	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764852337	3901551	0	0
T2	152191	2717	0	0
T3	2772	832	0	0
T4	46944	0	0	0
T5	66465	832	0	0
T6	694580	4973	0	0
T7	542489	5858	0	0
T8	17376	169	0	0
T9	22695	832	0	0
T10	1148834	832	0	0
T11	1758108	15394	0	0
T12	276236	9274	0	0
T13	66432	0	0	0
T14	122871	0	0	0
T15	606620	6373	0	0
T17	0	2933	0	0
T23	4088	152	0	0
T24	0	128	0	0
T25	0	117	0	0
T26	0	14	0	0
T30	0	9086	0	0
T37	0	9841	0	0
T43	0	527	0	0
T44	0	613	0	0
T45	0	6	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764852337	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764852337	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764852337	3901551	0	0
T2	152191	2717	0	0
T3	2772	832	0	0
T4	46944	0	0	0
T5	66465	832	0	0
T6	694580	4973	0	0
T7	542489	5858	0	0
T8	17376	169	0	0
T9	22695	832	0	0
T10	1148834	832	0	0
T11	1758108	15394	0	0
T12	276236	9274	0	0
T13	66432	0	0	0
T14	122871	0	0	0
T15	606620	6373	0	0
T17	0	2933	0	0
T23	4088	152	0	0
T24	0	128	0	0
T25	0	117	0	0
T26	0	14	0	0
T30	0	9086	0	0
T37	0	9841	0	0
T43	0	527	0	0
T44	0	613	0	0
T45	0	6	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764852337	3901551	0	0
T2	152191	2717	0	0
T3	2772	832	0	0
T4	46944	0	0	0
T5	66465	832	0	0
T6	694580	4973	0	0
T7	542489	5858	0	0
T8	17376	169	0	0
T9	22695	832	0	0
T10	1148834	832	0	0
T11	1758108	15394	0	0
T12	276236	9274	0	0
T13	66432	0	0	0
T14	122871	0	0	0
T15	606620	6373	0	0
T17	0	2933	0	0
T23	4088	152	0	0
T24	0	128	0	0
T25	0	117	0	0
T26	0	14	0	0
T30	0	9086	0	0
T37	0	9841	0	0
T43	0	527	0	0
T44	0	613	0	0
T45	0	6	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764852337	3901551	0	0
T2	152191	2717	0	0
T3	2772	832	0	0
T4	46944	0	0	0
T5	66465	832	0	0
T6	694580	4973	0	0
T7	542489	5858	0	0
T8	17376	169	0	0
T9	22695	832	0	0
T10	1148834	832	0	0
T11	1758108	15394	0	0
T12	276236	9274	0	0
T13	66432	0	0	0
T14	122871	0	0	0
T15	606620	6373	0	0
T17	0	2933	0	0
T23	4088	152	0	0
T24	0	128	0	0
T25	0	117	0	0
T26	0	14	0	0
T30	0	9086	0	0
T37	0	9841	0	0
T43	0	527	0	0
T44	0	613	0	0
T45	0	6	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	764852337	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764852337	6	0	956
T28	522436	0	0	1
T29	0	1	0	0
T46	504600	1	0	1
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	26988	0	0	1
T52	1857	0	0	1
T53	41738	0	0	1
T54	7775	0	0	1
T55	102661	0	0	1
T56	147323	0	0	1
T57	1208	0	0	1
T58	949005	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764852337	609673727	0	0
T1	5752	5536	0	0
T2	152191	151238	0	0
T3	2772	2716	0	0
T4	76266	46114	0	0
T5	102882	66241	0	0
T6	778960	694098	0	0
T7	542489	374484	0	0
T8	17376	15708	0	0
T9	22695	18523	0	0
T10	1148834	1005540	0	0
T11	1120406	555558	0	0
T12	276236	132232	0	0
T13	66432	66432	0	0
T14	0	122256	0	0
T15	0	601680	0	0
T16	0	48080	0	0
T17	0	51960	0	0
T23	0	3680	0	0
T24	0	3408	0	0
T25	0	1344	0	0
T26	0	712	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764852337	3901551	0	0
T2	152191	2717	0	0
T3	2772	832	0	0
T4	46944	0	0	0
T5	66465	832	0	0
T6	694580	4973	0	0
T7	542489	5858	0	0
T8	17376	169	0	0
T9	22695	832	0	0
T10	1148834	832	0	0
T11	1758108	15394	0	0
T12	276236	9274	0	0
T13	66432	0	0	0
T14	122871	0	0	0
T15	606620	6373	0	0
T17	0	2933	0	0
T23	4088	152	0	0
T24	0	128	0	0
T25	0	117	0	0
T26	0	14	0	0
T30	0	9086	0	0
T37	0	9841	0	0
T43	0	527	0	0
T44	0	613	0	0
T45	0	6	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T12
1	0	Covered	T7,T8,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T8
1	0	Unreachable
1	1	Covered	T7,T8,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T7,T8,T12
0	0	1	Unreachable
0	0	0	Covered	T4,T7,T8

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	153684665	29366154	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	153684665	670328	0	0
GntImpliesValid_A	153684665	670328	0	0
GrantKnown_A	153684665	29366154	0	0
IdxKnown_A	153684665	29366154	0	0
IndexIsCorrect_A	153684665	670328	0	0
LockArbDecision_A	153684665	0	0	0
NoReadyValidNoGrant_A	153684665	0	0	0
ReadyAndValidImplyGrant_A	153684665	670328	0	0
ReqAndReadyImplyGrant_A	153684665	670328	0	0
ReqImpliesValid_A	153684665	670328	0	0
ReqStaysHighUntilGranted0_M	153684665	0	0	0
RoundRobin_A	153684665	0	0	0
ValidKnown_A	153684665	29366154	0	0
gen_data_port_assertion.DataFlow_A	153684665	670328	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153684665	29366154	0	0
T4	29322	28552	0	0
T5	36417	0	0	0
T6	84380	0	0	0
T7	162251	156568	0	0
T8	1616	1616	0	0
T9	4112	0	0	0
T10	143200	0	0	0
T11	560203	0	0	0
T12	138118	132232	0	0
T13	66432	0	0	0
T15	0	324944	0	0
T17	0	51960	0	0
T23	0	3680	0	0
T24	0	3408	0	0
T25	0	1344	0	0
T26	0	712	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153684665	670328	0	0
T7	162251	4059	0	0
T8	1616	127	0	0
T9	4112	0	0	0
T10	143200	0	0	0
T11	560203	0	0	0
T12	138118	6326	0	0
T13	66432	0	0	0
T14	122871	0	0	0
T15	606620	3661	0	0
T17	0	2112	0	0
T23	4088	152	0	0
T24	0	128	0	0
T25	0	117	0	0
T26	0	14	0	0
T37	0	5134	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153684665	670328	0	0
T7	162251	4059	0	0
T8	1616	127	0	0
T9	4112	0	0	0
T10	143200	0	0	0
T11	560203	0	0	0
T12	138118	6326	0	0
T13	66432	0	0	0
T14	122871	0	0	0
T15	606620	3661	0	0
T17	0	2112	0	0
T23	4088	152	0	0
T24	0	128	0	0
T25	0	117	0	0
T26	0	14	0	0
T37	0	5134	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153684665	29366154	0	0
T4	29322	28552	0	0
T5	36417	0	0	0
T6	84380	0	0	0
T7	162251	156568	0	0
T8	1616	1616	0	0
T9	4112	0	0	0
T10	143200	0	0	0
T11	560203	0	0	0
T12	138118	132232	0	0
T13	66432	0	0	0
T15	0	324944	0	0
T17	0	51960	0	0
T23	0	3680	0	0
T24	0	3408	0	0
T25	0	1344	0	0
T26	0	712	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153684665	29366154	0	0
T4	29322	28552	0	0
T5	36417	0	0	0
T6	84380	0	0	0
T7	162251	156568	0	0
T8	1616	1616	0	0
T9	4112	0	0	0
T10	143200	0	0	0
T11	560203	0	0	0
T12	138118	132232	0	0
T13	66432	0	0	0
T15	0	324944	0	0
T17	0	51960	0	0
T23	0	3680	0	0
T24	0	3408	0	0
T25	0	1344	0	0
T26	0	712	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153684665	670328	0	0
T7	162251	4059	0	0
T8	1616	127	0	0
T9	4112	0	0	0
T10	143200	0	0	0
T11	560203	0	0	0
T12	138118	6326	0	0
T13	66432	0	0	0
T14	122871	0	0	0
T15	606620	3661	0	0
T17	0	2112	0	0
T23	4088	152	0	0
T24	0	128	0	0
T25	0	117	0	0
T26	0	14	0	0
T37	0	5134	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153684665	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153684665	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153684665	670328	0	0
T7	162251	4059	0	0
T8	1616	127	0	0
T9	4112	0	0	0
T10	143200	0	0	0
T11	560203	0	0	0
T12	138118	6326	0	0
T13	66432	0	0	0
T14	122871	0	0	0
T15	606620	3661	0	0
T17	0	2112	0	0
T23	4088	152	0	0
T24	0	128	0	0
T25	0	117	0	0
T26	0	14	0	0
T37	0	5134	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153684665	670328	0	0
T7	162251	4059	0	0
T8	1616	127	0	0
T9	4112	0	0	0
T10	143200	0	0	0
T11	560203	0	0	0
T12	138118	6326	0	0
T13	66432	0	0	0
T14	122871	0	0	0
T15	606620	3661	0	0
T17	0	2112	0	0
T23	4088	152	0	0
T24	0	128	0	0
T25	0	117	0	0
T26	0	14	0	0
T37	0	5134	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153684665	670328	0	0
T7	162251	4059	0	0
T8	1616	127	0	0
T9	4112	0	0	0
T10	143200	0	0	0
T11	560203	0	0	0
T12	138118	6326	0	0
T13	66432	0	0	0
T14	122871	0	0	0
T15	606620	3661	0	0
T17	0	2112	0	0
T23	4088	152	0	0
T24	0	128	0	0
T25	0	117	0	0
T26	0	14	0	0
T37	0	5134	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	153684665	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153684665	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153684665	29366154	0	0
T4	29322	28552	0	0
T5	36417	0	0	0
T6	84380	0	0	0
T7	162251	156568	0	0
T8	1616	1616	0	0
T9	4112	0	0	0
T10	143200	0	0	0
T11	560203	0	0	0
T12	138118	132232	0	0
T13	66432	0	0	0
T15	0	324944	0	0
T17	0	51960	0	0
T23	0	3680	0	0
T24	0	3408	0	0
T25	0	1344	0	0
T26	0	712	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153684665	670328	0	0
T7	162251	4059	0	0
T8	1616	127	0	0
T9	4112	0	0	0
T10	143200	0	0	0
T11	560203	0	0	0
T12	138118	6326	0	0
T13	66432	0	0	0
T14	122871	0	0	0
T15	606620	3661	0	0
T17	0	2112	0	0
T23	4088	152	0	0
T24	0	128	0	0
T25	0	117	0	0
T26	0	14	0	0
T37	0	5134	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T11

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T6,T11
1	0	Covered	T2,T6,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Unreachable
1	1	Covered	T2,T6,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T6,T11
0	0	1	Unreachable
0	0	0	Covered	T2,T5,T6

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	153684665	122910776	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	153684665	901802	0	0
GntImpliesValid_A	153684665	901802	0	0
GrantKnown_A	153684665	122910776	0	0
IdxKnown_A	153684665	122910776	0	0
IndexIsCorrect_A	153684665	901802	0	0
LockArbDecision_A	153684665	0	0	0
NoReadyValidNoGrant_A	153684665	0	0	0
ReadyAndValidImplyGrant_A	153684665	901802	0	0
ReqAndReadyImplyGrant_A	153684665	901802	0	0
ReqImpliesValid_A	153684665	901802	0	0
ReqStaysHighUntilGranted0_M	153684665	0	0	0
RoundRobin_A	153684665	0	0	0
ValidKnown_A	153684665	122910776	0	0
gen_data_port_assertion.DataFlow_A	153684665	901802	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153684665	122910776	0	0
T2	95620	94765	0	0
T4	29322	0	0	0
T5	36417	36268	0	0
T6	84380	83979	0	0
T7	162251	0	0	0
T8	1616	0	0	0
T9	4112	4112	0	0
T10	143200	143200	0	0
T11	560203	555558	0	0
T12	138118	0	0	0
T13	0	66432	0	0
T14	0	122256	0	0
T15	0	276736	0	0
T16	0	48080	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153684665	901802	0	0
T2	95620	169	0	0
T4	29322	0	0	0
T5	36417	0	0	0
T6	84380	3110	0	0
T7	162251	0	0	0
T8	1616	0	0	0
T9	4112	0	0	0
T10	143200	0	0	0
T11	560203	4077	0	0
T12	138118	0	0	0
T15	0	2712	0	0
T17	0	821	0	0
T30	0	9086	0	0
T37	0	4707	0	0
T43	0	527	0	0
T44	0	613	0	0
T45	0	6	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153684665	901802	0	0
T2	95620	169	0	0
T4	29322	0	0	0
T5	36417	0	0	0
T6	84380	3110	0	0
T7	162251	0	0	0
T8	1616	0	0	0
T9	4112	0	0	0
T10	143200	0	0	0
T11	560203	4077	0	0
T12	138118	0	0	0
T15	0	2712	0	0
T17	0	821	0	0
T30	0	9086	0	0
T37	0	4707	0	0
T43	0	527	0	0
T44	0	613	0	0
T45	0	6	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153684665	122910776	0	0
T2	95620	94765	0	0
T4	29322	0	0	0
T5	36417	36268	0	0
T6	84380	83979	0	0
T7	162251	0	0	0
T8	1616	0	0	0
T9	4112	4112	0	0
T10	143200	143200	0	0
T11	560203	555558	0	0
T12	138118	0	0	0
T13	0	66432	0	0
T14	0	122256	0	0
T15	0	276736	0	0
T16	0	48080	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153684665	122910776	0	0
T2	95620	94765	0	0
T4	29322	0	0	0
T5	36417	36268	0	0
T6	84380	83979	0	0
T7	162251	0	0	0
T8	1616	0	0	0
T9	4112	4112	0	0
T10	143200	143200	0	0
T11	560203	555558	0	0
T12	138118	0	0	0
T13	0	66432	0	0
T14	0	122256	0	0
T15	0	276736	0	0
T16	0	48080	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153684665	901802	0	0
T2	95620	169	0	0
T4	29322	0	0	0
T5	36417	0	0	0
T6	84380	3110	0	0
T7	162251	0	0	0
T8	1616	0	0	0
T9	4112	0	0	0
T10	143200	0	0	0
T11	560203	4077	0	0
T12	138118	0	0	0
T15	0	2712	0	0
T17	0	821	0	0
T30	0	9086	0	0
T37	0	4707	0	0
T43	0	527	0	0
T44	0	613	0	0
T45	0	6	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153684665	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153684665	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153684665	901802	0	0
T2	95620	169	0	0
T4	29322	0	0	0
T5	36417	0	0	0
T6	84380	3110	0	0
T7	162251	0	0	0
T8	1616	0	0	0
T9	4112	0	0	0
T10	143200	0	0	0
T11	560203	4077	0	0
T12	138118	0	0	0
T15	0	2712	0	0
T17	0	821	0	0
T30	0	9086	0	0
T37	0	4707	0	0
T43	0	527	0	0
T44	0	613	0	0
T45	0	6	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153684665	901802	0	0
T2	95620	169	0	0
T4	29322	0	0	0
T5	36417	0	0	0
T6	84380	3110	0	0
T7	162251	0	0	0
T8	1616	0	0	0
T9	4112	0	0	0
T10	143200	0	0	0
T11	560203	4077	0	0
T12	138118	0	0	0
T15	0	2712	0	0
T17	0	821	0	0
T30	0	9086	0	0
T37	0	4707	0	0
T43	0	527	0	0
T44	0	613	0	0
T45	0	6	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153684665	901802	0	0
T2	95620	169	0	0
T4	29322	0	0	0
T5	36417	0	0	0
T6	84380	3110	0	0
T7	162251	0	0	0
T8	1616	0	0	0
T9	4112	0	0	0
T10	143200	0	0	0
T11	560203	4077	0	0
T12	138118	0	0	0
T15	0	2712	0	0
T17	0	821	0	0
T30	0	9086	0	0
T37	0	4707	0	0
T43	0	527	0	0
T44	0	613	0	0
T45	0	6	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	153684665	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153684665	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153684665	122910776	0	0
T2	95620	94765	0	0
T4	29322	0	0	0
T5	36417	36268	0	0
T6	84380	83979	0	0
T7	162251	0	0	0
T8	1616	0	0	0
T9	4112	4112	0	0
T10	143200	143200	0	0
T11	560203	555558	0	0
T12	138118	0	0	0
T13	0	66432	0	0
T14	0	122256	0	0
T15	0	276736	0	0
T16	0	48080	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153684665	901802	0	0
T2	95620	169	0	0
T4	29322	0	0	0
T5	36417	0	0	0
T6	84380	3110	0	0
T7	162251	0	0	0
T8	1616	0	0	0
T9	4112	0	0	0
T10	143200	0	0	0
T11	560203	4077	0	0
T12	138118	0	0	0
T15	0	2712	0	0
T17	0	821	0	0
T30	0	9086	0	0
T37	0	4707	0	0
T43	0	527	0	0
T44	0	613	0	0
T45	0	6	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T6,T7
1	0	Covered	T2,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	457483007	457396797	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	457483007	2329421	0	0
GntImpliesValid_A	457483007	2329421	0	0
GrantKnown_A	457483007	457396797	0	0
IdxKnown_A	457483007	457396797	0	0
IndexIsCorrect_A	457483007	2329421	0	0
LockArbDecision_A	457483007	0	0	0
NoReadyValidNoGrant_A	457483007	0	0	0
ReadyAndValidImplyGrant_A	457483007	2329421	0	0
ReqAndReadyImplyGrant_A	457483007	2329421	0	0
ReqImpliesValid_A	457483007	2329421	0	0
ReqStaysHighUntilGranted0_M	457483007	0	0	0
RoundRobin_A	457483007	6	0	956
ValidKnown_A	457483007	457396797	0	0
gen_data_port_assertion.DataFlow_A	457483007	2329421	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457483007	457396797	0	0
T1	5752	5536	0	0
T2	56571	56473	0	0
T3	2772	2716	0	0
T4	17622	17562	0	0
T5	30048	29973	0	0
T6	610200	610119	0	0
T7	217987	217916	0	0
T8	14144	14092	0	0
T9	14471	14411	0	0
T10	862434	862340	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457483007	2329421	0	0
T2	56571	2548	0	0
T3	2772	832	0	0
T4	17622	0	0	0
T5	30048	832	0	0
T6	610200	1863	0	0
T7	217987	1799	0	0
T8	14144	42	0	0
T9	14471	832	0	0
T10	862434	832	0	0
T11	637702	11317	0	0
T12	0	2948	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457483007	2329421	0	0
T2	56571	2548	0	0
T3	2772	832	0	0
T4	17622	0	0	0
T5	30048	832	0	0
T6	610200	1863	0	0
T7	217987	1799	0	0
T8	14144	42	0	0
T9	14471	832	0	0
T10	862434	832	0	0
T11	637702	11317	0	0
T12	0	2948	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457483007	457396797	0	0
T1	5752	5536	0	0
T2	56571	56473	0	0
T3	2772	2716	0	0
T4	17622	17562	0	0
T5	30048	29973	0	0
T6	610200	610119	0	0
T7	217987	217916	0	0
T8	14144	14092	0	0
T9	14471	14411	0	0
T10	862434	862340	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457483007	457396797	0	0
T1	5752	5536	0	0
T2	56571	56473	0	0
T3	2772	2716	0	0
T4	17622	17562	0	0
T5	30048	29973	0	0
T6	610200	610119	0	0
T7	217987	217916	0	0
T8	14144	14092	0	0
T9	14471	14411	0	0
T10	862434	862340	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457483007	2329421	0	0
T2	56571	2548	0	0
T3	2772	832	0	0
T4	17622	0	0	0
T5	30048	832	0	0
T6	610200	1863	0	0
T7	217987	1799	0	0
T8	14144	42	0	0
T9	14471	832	0	0
T10	862434	832	0	0
T11	637702	11317	0	0
T12	0	2948	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457483007	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457483007	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457483007	2329421	0	0
T2	56571	2548	0	0
T3	2772	832	0	0
T4	17622	0	0	0
T5	30048	832	0	0
T6	610200	1863	0	0
T7	217987	1799	0	0
T8	14144	42	0	0
T9	14471	832	0	0
T10	862434	832	0	0
T11	637702	11317	0	0
T12	0	2948	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457483007	2329421	0	0
T2	56571	2548	0	0
T3	2772	832	0	0
T4	17622	0	0	0
T5	30048	832	0	0
T6	610200	1863	0	0
T7	217987	1799	0	0
T8	14144	42	0	0
T9	14471	832	0	0
T10	862434	832	0	0
T11	637702	11317	0	0
T12	0	2948	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457483007	2329421	0	0
T2	56571	2548	0	0
T3	2772	832	0	0
T4	17622	0	0	0
T5	30048	832	0	0
T6	610200	1863	0	0
T7	217987	1799	0	0
T8	14144	42	0	0
T9	14471	832	0	0
T10	862434	832	0	0
T11	637702	11317	0	0
T12	0	2948	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	457483007	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457483007	6	0	956
T28	522436	0	0	1
T29	0	1	0	0
T46	504600	1	0	1
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	26988	0	0	1
T52	1857	0	0	1
T53	41738	0	0	1
T54	7775	0	0	1
T55	102661	0	0	1
T56	147323	0	0	1
T57	1208	0	0	1
T58	949005	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457483007	457396797	0	0
T1	5752	5536	0	0
T2	56571	56473	0	0
T3	2772	2716	0	0
T4	17622	17562	0	0
T5	30048	29973	0	0
T6	610200	610119	0	0
T7	217987	217916	0	0
T8	14144	14092	0	0
T9	14471	14411	0	0
T10	862434	862340	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457483007	2329421	0	0
T2	56571	2548	0	0
T3	2772	832	0	0
T4	17622	0	0	0
T5	30048	832	0	0
T6	610200	1863	0	0
T7	217987	1799	0	0
T8	14144	42	0	0
T9	14471	832	0	0
T10	862434	832	0	0
T11	637702	11317	0	0
T12	0	2948	0	0