Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
3245 |
0 |
0 |
T63 |
3822 |
8 |
0 |
0 |
T64 |
12301 |
240 |
0 |
0 |
T65 |
63808 |
3 |
0 |
0 |
T100 |
5007 |
6 |
0 |
0 |
T101 |
20000 |
6 |
0 |
0 |
T102 |
55979 |
1 |
0 |
0 |
T103 |
6900 |
100 |
0 |
0 |
T114 |
5905 |
1 |
0 |
0 |
T115 |
20947 |
1 |
0 |
0 |
T116 |
68927 |
2 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
2152 |
0 |
0 |
T65 |
63808 |
76 |
0 |
0 |
T116 |
68927 |
68 |
0 |
0 |
T120 |
6885 |
1 |
0 |
0 |
T122 |
269334 |
726 |
0 |
0 |
T123 |
116470 |
725 |
0 |
0 |
T148 |
19343 |
89 |
0 |
0 |
T155 |
7298 |
11 |
0 |
0 |
T156 |
67116 |
63 |
0 |
0 |
T157 |
18084 |
70 |
0 |
0 |
T158 |
16176 |
24 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
2058 |
0 |
0 |
T65 |
63808 |
73 |
0 |
0 |
T114 |
5905 |
8 |
0 |
0 |
T116 |
68927 |
72 |
0 |
0 |
T120 |
6885 |
4 |
0 |
0 |
T122 |
269334 |
618 |
0 |
0 |
T123 |
116470 |
785 |
0 |
0 |
T148 |
19343 |
58 |
0 |
0 |
T155 |
7298 |
5 |
0 |
0 |
T156 |
67116 |
89 |
0 |
0 |
T157 |
18084 |
42 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
2325 |
0 |
0 |
T65 |
63808 |
138 |
0 |
0 |
T114 |
5905 |
2 |
0 |
0 |
T116 |
68927 |
144 |
0 |
0 |
T120 |
6885 |
7 |
0 |
0 |
T122 |
269334 |
623 |
0 |
0 |
T123 |
116470 |
748 |
0 |
0 |
T148 |
19343 |
20 |
0 |
0 |
T155 |
7298 |
27 |
0 |
0 |
T156 |
67116 |
154 |
0 |
0 |
T157 |
18084 |
25 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
7886 |
0 |
0 |
T65 |
63808 |
603 |
0 |
0 |
T114 |
5905 |
89 |
0 |
0 |
T116 |
68927 |
1757 |
0 |
0 |
T122 |
269334 |
663 |
0 |
0 |
T123 |
116470 |
756 |
0 |
0 |
T148 |
19343 |
81 |
0 |
0 |
T155 |
7298 |
134 |
0 |
0 |
T156 |
67116 |
1232 |
0 |
0 |
T157 |
18084 |
47 |
0 |
0 |
T158 |
16176 |
338 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
7124 |
0 |
0 |
T65 |
63808 |
1177 |
0 |
0 |
T114 |
5905 |
67 |
0 |
0 |
T116 |
68927 |
960 |
0 |
0 |
T120 |
6885 |
71 |
0 |
0 |
T122 |
269334 |
665 |
0 |
0 |
T123 |
116470 |
697 |
0 |
0 |
T148 |
19343 |
23 |
0 |
0 |
T155 |
7298 |
152 |
0 |
0 |
T156 |
67116 |
1042 |
0 |
0 |
T157 |
18084 |
50 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
6957 |
0 |
0 |
T65 |
63808 |
860 |
0 |
0 |
T114 |
5905 |
43 |
0 |
0 |
T116 |
68927 |
1442 |
0 |
0 |
T120 |
6885 |
61 |
0 |
0 |
T122 |
269334 |
684 |
0 |
0 |
T123 |
116470 |
741 |
0 |
0 |
T148 |
19343 |
54 |
0 |
0 |
T155 |
7298 |
104 |
0 |
0 |
T156 |
67116 |
1126 |
0 |
0 |
T157 |
18084 |
59 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
8589 |
0 |
0 |
T65 |
63808 |
1047 |
0 |
0 |
T116 |
68927 |
1449 |
0 |
0 |
T120 |
6885 |
115 |
0 |
0 |
T122 |
269334 |
607 |
0 |
0 |
T123 |
116470 |
747 |
0 |
0 |
T148 |
19343 |
92 |
0 |
0 |
T155 |
7298 |
240 |
0 |
0 |
T156 |
67116 |
1073 |
0 |
0 |
T157 |
18084 |
46 |
0 |
0 |
T158 |
16176 |
396 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
7404 |
0 |
0 |
T65 |
63808 |
1213 |
0 |
0 |
T114 |
5905 |
72 |
0 |
0 |
T116 |
68927 |
1256 |
0 |
0 |
T120 |
6885 |
47 |
0 |
0 |
T122 |
269334 |
683 |
0 |
0 |
T123 |
116470 |
729 |
0 |
0 |
T148 |
19343 |
80 |
0 |
0 |
T155 |
7298 |
16 |
0 |
0 |
T156 |
67116 |
1059 |
0 |
0 |
T157 |
18084 |
55 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
8152 |
0 |
0 |
T65 |
63808 |
896 |
0 |
0 |
T114 |
5905 |
1 |
0 |
0 |
T116 |
68927 |
1182 |
0 |
0 |
T120 |
6885 |
162 |
0 |
0 |
T122 |
269334 |
681 |
0 |
0 |
T123 |
116470 |
740 |
0 |
0 |
T148 |
19343 |
81 |
0 |
0 |
T155 |
7298 |
14 |
0 |
0 |
T156 |
67116 |
1580 |
0 |
0 |
T157 |
18084 |
26 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
8481 |
0 |
0 |
T65 |
63808 |
1172 |
0 |
0 |
T114 |
5905 |
15 |
0 |
0 |
T116 |
68927 |
1420 |
0 |
0 |
T120 |
6885 |
80 |
0 |
0 |
T122 |
269334 |
708 |
0 |
0 |
T123 |
116470 |
651 |
0 |
0 |
T148 |
19343 |
124 |
0 |
0 |
T155 |
7298 |
5 |
0 |
0 |
T156 |
67116 |
1565 |
0 |
0 |
T157 |
18084 |
42 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
7869 |
0 |
0 |
T65 |
63808 |
735 |
0 |
0 |
T114 |
5905 |
5 |
0 |
0 |
T116 |
68927 |
1239 |
0 |
0 |
T120 |
6885 |
148 |
0 |
0 |
T122 |
269334 |
651 |
0 |
0 |
T123 |
116470 |
732 |
0 |
0 |
T148 |
19343 |
58 |
0 |
0 |
T155 |
7298 |
267 |
0 |
0 |
T156 |
67116 |
1208 |
0 |
0 |
T157 |
18084 |
45 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
4122 |
0 |
0 |
T65 |
63808 |
509 |
0 |
0 |
T116 |
68927 |
591 |
0 |
0 |
T120 |
6885 |
63 |
0 |
0 |
T122 |
269334 |
601 |
0 |
0 |
T123 |
116470 |
744 |
0 |
0 |
T148 |
19343 |
122 |
0 |
0 |
T155 |
7298 |
63 |
0 |
0 |
T156 |
67116 |
378 |
0 |
0 |
T157 |
18084 |
52 |
0 |
0 |
T158 |
16176 |
70 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
4326 |
0 |
0 |
T65 |
63808 |
508 |
0 |
0 |
T114 |
5905 |
21 |
0 |
0 |
T116 |
68927 |
473 |
0 |
0 |
T120 |
6885 |
33 |
0 |
0 |
T122 |
269334 |
667 |
0 |
0 |
T123 |
116470 |
779 |
0 |
0 |
T148 |
19343 |
34 |
0 |
0 |
T155 |
7298 |
71 |
0 |
0 |
T156 |
67116 |
706 |
0 |
0 |
T157 |
18084 |
2 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
3910 |
0 |
0 |
T65 |
63808 |
517 |
0 |
0 |
T114 |
5905 |
29 |
0 |
0 |
T116 |
68927 |
424 |
0 |
0 |
T120 |
6885 |
11 |
0 |
0 |
T122 |
269334 |
748 |
0 |
0 |
T123 |
116470 |
740 |
0 |
0 |
T148 |
19343 |
33 |
0 |
0 |
T155 |
7298 |
133 |
0 |
0 |
T156 |
67116 |
506 |
0 |
0 |
T158 |
16176 |
72 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
3873 |
0 |
0 |
T65 |
63808 |
410 |
0 |
0 |
T114 |
5905 |
34 |
0 |
0 |
T116 |
68927 |
363 |
0 |
0 |
T120 |
6885 |
5 |
0 |
0 |
T122 |
269334 |
672 |
0 |
0 |
T123 |
116470 |
698 |
0 |
0 |
T148 |
19343 |
86 |
0 |
0 |
T155 |
7298 |
76 |
0 |
0 |
T156 |
67116 |
372 |
0 |
0 |
T157 |
18084 |
33 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
4405 |
0 |
0 |
T65 |
63808 |
501 |
0 |
0 |
T114 |
5905 |
42 |
0 |
0 |
T116 |
68927 |
662 |
0 |
0 |
T122 |
269334 |
633 |
0 |
0 |
T123 |
116470 |
677 |
0 |
0 |
T148 |
19343 |
27 |
0 |
0 |
T155 |
7298 |
103 |
0 |
0 |
T156 |
67116 |
461 |
0 |
0 |
T157 |
18084 |
67 |
0 |
0 |
T158 |
16176 |
104 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
4359 |
0 |
0 |
T65 |
63808 |
418 |
0 |
0 |
T114 |
5905 |
36 |
0 |
0 |
T116 |
68927 |
541 |
0 |
0 |
T120 |
6885 |
32 |
0 |
0 |
T122 |
269334 |
681 |
0 |
0 |
T123 |
116470 |
733 |
0 |
0 |
T148 |
19343 |
55 |
0 |
0 |
T155 |
7298 |
8 |
0 |
0 |
T156 |
67116 |
583 |
0 |
0 |
T157 |
18084 |
59 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
4117 |
0 |
0 |
T65 |
63808 |
471 |
0 |
0 |
T114 |
5905 |
35 |
0 |
0 |
T116 |
68927 |
603 |
0 |
0 |
T120 |
6885 |
4 |
0 |
0 |
T122 |
269334 |
653 |
0 |
0 |
T123 |
116470 |
747 |
0 |
0 |
T148 |
19343 |
77 |
0 |
0 |
T155 |
7298 |
9 |
0 |
0 |
T156 |
67116 |
435 |
0 |
0 |
T157 |
18084 |
30 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
4500 |
0 |
0 |
T65 |
63808 |
484 |
0 |
0 |
T114 |
5905 |
9 |
0 |
0 |
T116 |
68927 |
721 |
0 |
0 |
T120 |
6885 |
18 |
0 |
0 |
T122 |
269334 |
674 |
0 |
0 |
T123 |
116470 |
814 |
0 |
0 |
T148 |
19343 |
63 |
0 |
0 |
T155 |
7298 |
5 |
0 |
0 |
T156 |
67116 |
775 |
0 |
0 |
T157 |
18084 |
39 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
4508 |
0 |
0 |
T65 |
63808 |
604 |
0 |
0 |
T114 |
5905 |
18 |
0 |
0 |
T116 |
68927 |
597 |
0 |
0 |
T120 |
6885 |
36 |
0 |
0 |
T122 |
269334 |
694 |
0 |
0 |
T123 |
116470 |
750 |
0 |
0 |
T148 |
19343 |
28 |
0 |
0 |
T155 |
7298 |
2 |
0 |
0 |
T156 |
67116 |
863 |
0 |
0 |
T157 |
18084 |
20 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
4277 |
0 |
0 |
T65 |
63808 |
538 |
0 |
0 |
T114 |
5905 |
49 |
0 |
0 |
T116 |
68927 |
472 |
0 |
0 |
T120 |
6885 |
5 |
0 |
0 |
T122 |
269334 |
708 |
0 |
0 |
T123 |
116470 |
771 |
0 |
0 |
T148 |
19343 |
84 |
0 |
0 |
T155 |
7298 |
122 |
0 |
0 |
T156 |
67116 |
541 |
0 |
0 |
T157 |
18084 |
37 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
4331 |
0 |
0 |
T65 |
63808 |
315 |
0 |
0 |
T114 |
5905 |
4 |
0 |
0 |
T116 |
68927 |
698 |
0 |
0 |
T120 |
6885 |
18 |
0 |
0 |
T122 |
269334 |
668 |
0 |
0 |
T123 |
116470 |
754 |
0 |
0 |
T148 |
19343 |
76 |
0 |
0 |
T155 |
7298 |
10 |
0 |
0 |
T156 |
67116 |
469 |
0 |
0 |
T157 |
18084 |
53 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
4712 |
0 |
0 |
T65 |
63808 |
678 |
0 |
0 |
T114 |
5905 |
21 |
0 |
0 |
T116 |
68927 |
470 |
0 |
0 |
T120 |
6885 |
24 |
0 |
0 |
T122 |
269334 |
731 |
0 |
0 |
T123 |
116470 |
779 |
0 |
0 |
T148 |
19343 |
60 |
0 |
0 |
T155 |
7298 |
59 |
0 |
0 |
T156 |
67116 |
645 |
0 |
0 |
T157 |
18084 |
10 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
4476 |
0 |
0 |
T65 |
63808 |
495 |
0 |
0 |
T114 |
5905 |
31 |
0 |
0 |
T116 |
68927 |
618 |
0 |
0 |
T120 |
6885 |
45 |
0 |
0 |
T122 |
269334 |
679 |
0 |
0 |
T123 |
116470 |
730 |
0 |
0 |
T148 |
19343 |
84 |
0 |
0 |
T155 |
7298 |
107 |
0 |
0 |
T156 |
67116 |
607 |
0 |
0 |
T157 |
18084 |
45 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
4359 |
0 |
0 |
T65 |
63808 |
402 |
0 |
0 |
T114 |
5905 |
30 |
0 |
0 |
T116 |
68927 |
672 |
0 |
0 |
T120 |
6885 |
28 |
0 |
0 |
T122 |
269334 |
673 |
0 |
0 |
T123 |
116470 |
699 |
0 |
0 |
T148 |
19343 |
36 |
0 |
0 |
T155 |
7298 |
39 |
0 |
0 |
T156 |
67116 |
684 |
0 |
0 |
T157 |
18084 |
55 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
4335 |
0 |
0 |
T65 |
63808 |
492 |
0 |
0 |
T114 |
5905 |
1 |
0 |
0 |
T116 |
68927 |
661 |
0 |
0 |
T120 |
6885 |
8 |
0 |
0 |
T122 |
269334 |
672 |
0 |
0 |
T123 |
116470 |
768 |
0 |
0 |
T148 |
19343 |
54 |
0 |
0 |
T155 |
7298 |
9 |
0 |
0 |
T156 |
67116 |
501 |
0 |
0 |
T157 |
18084 |
4 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
4465 |
0 |
0 |
T65 |
63808 |
427 |
0 |
0 |
T114 |
5905 |
35 |
0 |
0 |
T116 |
68927 |
681 |
0 |
0 |
T120 |
6885 |
24 |
0 |
0 |
T122 |
269334 |
700 |
0 |
0 |
T123 |
116470 |
740 |
0 |
0 |
T148 |
19343 |
44 |
0 |
0 |
T155 |
7298 |
68 |
0 |
0 |
T156 |
67116 |
628 |
0 |
0 |
T157 |
18084 |
95 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
4524 |
0 |
0 |
T65 |
63808 |
628 |
0 |
0 |
T116 |
68927 |
559 |
0 |
0 |
T120 |
6885 |
2 |
0 |
0 |
T122 |
269334 |
714 |
0 |
0 |
T123 |
116470 |
807 |
0 |
0 |
T148 |
19343 |
97 |
0 |
0 |
T155 |
7298 |
63 |
0 |
0 |
T156 |
67116 |
526 |
0 |
0 |
T157 |
18084 |
23 |
0 |
0 |
T158 |
16176 |
102 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
4068 |
0 |
0 |
T65 |
63808 |
396 |
0 |
0 |
T114 |
5905 |
23 |
0 |
0 |
T116 |
68927 |
528 |
0 |
0 |
T120 |
6885 |
2 |
0 |
0 |
T122 |
269334 |
682 |
0 |
0 |
T123 |
116470 |
707 |
0 |
0 |
T148 |
19343 |
27 |
0 |
0 |
T155 |
7298 |
2 |
0 |
0 |
T156 |
67116 |
591 |
0 |
0 |
T157 |
18084 |
61 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
3912 |
0 |
0 |
T65 |
63808 |
512 |
0 |
0 |
T114 |
5905 |
3 |
0 |
0 |
T116 |
68927 |
593 |
0 |
0 |
T120 |
6885 |
47 |
0 |
0 |
T122 |
269334 |
694 |
0 |
0 |
T123 |
116470 |
625 |
0 |
0 |
T148 |
19343 |
84 |
0 |
0 |
T155 |
7298 |
61 |
0 |
0 |
T156 |
67116 |
367 |
0 |
0 |
T157 |
18084 |
31 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
3883 |
0 |
0 |
T65 |
63808 |
341 |
0 |
0 |
T114 |
5905 |
30 |
0 |
0 |
T116 |
68927 |
503 |
0 |
0 |
T120 |
6885 |
33 |
0 |
0 |
T122 |
269334 |
708 |
0 |
0 |
T123 |
116470 |
754 |
0 |
0 |
T148 |
19343 |
46 |
0 |
0 |
T155 |
7298 |
10 |
0 |
0 |
T156 |
67116 |
505 |
0 |
0 |
T157 |
18084 |
38 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
4339 |
0 |
0 |
T65 |
63808 |
472 |
0 |
0 |
T116 |
68927 |
628 |
0 |
0 |
T120 |
6885 |
2 |
0 |
0 |
T122 |
269334 |
671 |
0 |
0 |
T123 |
116470 |
790 |
0 |
0 |
T148 |
19343 |
72 |
0 |
0 |
T155 |
7298 |
52 |
0 |
0 |
T156 |
67116 |
496 |
0 |
0 |
T157 |
18084 |
25 |
0 |
0 |
T158 |
16176 |
141 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
4819 |
0 |
0 |
T65 |
63808 |
481 |
0 |
0 |
T114 |
5905 |
20 |
0 |
0 |
T116 |
68927 |
770 |
0 |
0 |
T120 |
6885 |
41 |
0 |
0 |
T122 |
269334 |
720 |
0 |
0 |
T123 |
116470 |
726 |
0 |
0 |
T148 |
19343 |
121 |
0 |
0 |
T155 |
7298 |
67 |
0 |
0 |
T156 |
67116 |
663 |
0 |
0 |
T157 |
18084 |
26 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
4184 |
0 |
0 |
T65 |
63808 |
466 |
0 |
0 |
T114 |
5905 |
1 |
0 |
0 |
T116 |
68927 |
513 |
0 |
0 |
T120 |
6885 |
44 |
0 |
0 |
T122 |
269334 |
641 |
0 |
0 |
T123 |
116470 |
728 |
0 |
0 |
T148 |
19343 |
80 |
0 |
0 |
T155 |
7298 |
36 |
0 |
0 |
T156 |
67116 |
490 |
0 |
0 |
T157 |
18084 |
19 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
4361 |
0 |
0 |
T65 |
63808 |
645 |
0 |
0 |
T114 |
5905 |
55 |
0 |
0 |
T116 |
68927 |
442 |
0 |
0 |
T120 |
6885 |
17 |
0 |
0 |
T122 |
269334 |
665 |
0 |
0 |
T123 |
116470 |
711 |
0 |
0 |
T148 |
19343 |
65 |
0 |
0 |
T155 |
7298 |
85 |
0 |
0 |
T156 |
67116 |
517 |
0 |
0 |
T157 |
18084 |
55 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
2250 |
0 |
0 |
T65 |
63808 |
111 |
0 |
0 |
T114 |
5905 |
9 |
0 |
0 |
T116 |
68927 |
101 |
0 |
0 |
T120 |
6885 |
2 |
0 |
0 |
T122 |
269334 |
715 |
0 |
0 |
T123 |
116470 |
715 |
0 |
0 |
T148 |
19343 |
52 |
0 |
0 |
T155 |
7298 |
24 |
0 |
0 |
T156 |
67116 |
117 |
0 |
0 |
T157 |
18084 |
63 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
2316 |
0 |
0 |
T65 |
63808 |
91 |
0 |
0 |
T114 |
5905 |
4 |
0 |
0 |
T116 |
68927 |
135 |
0 |
0 |
T120 |
6885 |
11 |
0 |
0 |
T122 |
269334 |
636 |
0 |
0 |
T123 |
116470 |
732 |
0 |
0 |
T148 |
19343 |
47 |
0 |
0 |
T155 |
7298 |
12 |
0 |
0 |
T156 |
67116 |
141 |
0 |
0 |
T157 |
18084 |
52 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
2391 |
0 |
0 |
T65 |
63808 |
107 |
0 |
0 |
T114 |
5905 |
1 |
0 |
0 |
T116 |
68927 |
154 |
0 |
0 |
T120 |
6885 |
5 |
0 |
0 |
T122 |
269334 |
681 |
0 |
0 |
T123 |
116470 |
753 |
0 |
0 |
T148 |
19343 |
94 |
0 |
0 |
T155 |
7298 |
23 |
0 |
0 |
T156 |
67116 |
117 |
0 |
0 |
T157 |
18084 |
54 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
2130 |
0 |
0 |
T65 |
63808 |
79 |
0 |
0 |
T114 |
5905 |
10 |
0 |
0 |
T116 |
68927 |
125 |
0 |
0 |
T120 |
6885 |
2 |
0 |
0 |
T122 |
269334 |
663 |
0 |
0 |
T123 |
116470 |
687 |
0 |
0 |
T148 |
19343 |
52 |
0 |
0 |
T155 |
7298 |
15 |
0 |
0 |
T156 |
67116 |
141 |
0 |
0 |
T157 |
18084 |
45 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
2540 |
0 |
0 |
T65 |
63808 |
166 |
0 |
0 |
T114 |
5905 |
6 |
0 |
0 |
T116 |
68927 |
187 |
0 |
0 |
T120 |
6885 |
8 |
0 |
0 |
T122 |
269334 |
649 |
0 |
0 |
T123 |
116470 |
759 |
0 |
0 |
T148 |
19343 |
44 |
0 |
0 |
T155 |
7298 |
26 |
0 |
0 |
T156 |
67116 |
138 |
0 |
0 |
T157 |
18084 |
53 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
3786 |
0 |
0 |
T12 |
992996 |
27 |
0 |
0 |
T13 |
468958 |
0 |
0 |
0 |
T14 |
40312 |
0 |
0 |
0 |
T15 |
181844 |
0 |
0 |
0 |
T16 |
396057 |
0 |
0 |
0 |
T17 |
108152 |
13 |
0 |
0 |
T22 |
0 |
8 |
0 |
0 |
T23 |
3030 |
0 |
0 |
0 |
T27 |
0 |
29 |
0 |
0 |
T28 |
0 |
63 |
0 |
0 |
T29 |
0 |
10 |
0 |
0 |
T36 |
38181 |
0 |
0 |
0 |
T38 |
28205 |
0 |
0 |
0 |
T60 |
943 |
0 |
0 |
0 |
T85 |
0 |
30 |
0 |
0 |
T159 |
0 |
105 |
0 |
0 |
T160 |
0 |
44 |
0 |
0 |
T161 |
0 |
53 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
2208 |
0 |
0 |
T65 |
63808 |
102 |
0 |
0 |
T114 |
5905 |
6 |
0 |
0 |
T116 |
68927 |
100 |
0 |
0 |
T120 |
6885 |
12 |
0 |
0 |
T122 |
269334 |
657 |
0 |
0 |
T123 |
116470 |
704 |
0 |
0 |
T148 |
19343 |
32 |
0 |
0 |
T155 |
7298 |
13 |
0 |
0 |
T156 |
67116 |
120 |
0 |
0 |
T157 |
18084 |
44 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
2222 |
0 |
0 |
T65 |
63808 |
112 |
0 |
0 |
T114 |
5905 |
7 |
0 |
0 |
T116 |
68927 |
127 |
0 |
0 |
T122 |
269334 |
617 |
0 |
0 |
T123 |
116470 |
725 |
0 |
0 |
T148 |
19343 |
54 |
0 |
0 |
T155 |
7298 |
13 |
0 |
0 |
T156 |
67116 |
109 |
0 |
0 |
T157 |
18084 |
42 |
0 |
0 |
T158 |
16176 |
37 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
1979 |
0 |
0 |
T65 |
63808 |
64 |
0 |
0 |
T114 |
5905 |
7 |
0 |
0 |
T116 |
68927 |
96 |
0 |
0 |
T120 |
6885 |
4 |
0 |
0 |
T122 |
269334 |
590 |
0 |
0 |
T123 |
116470 |
778 |
0 |
0 |
T148 |
19343 |
38 |
0 |
0 |
T155 |
7298 |
14 |
0 |
0 |
T156 |
67116 |
68 |
0 |
0 |
T157 |
18084 |
17 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
2104 |
0 |
0 |
T65 |
63808 |
57 |
0 |
0 |
T114 |
5905 |
9 |
0 |
0 |
T116 |
68927 |
61 |
0 |
0 |
T120 |
6885 |
2 |
0 |
0 |
T122 |
269334 |
728 |
0 |
0 |
T123 |
116470 |
754 |
0 |
0 |
T148 |
19343 |
23 |
0 |
0 |
T155 |
7298 |
15 |
0 |
0 |
T156 |
67116 |
78 |
0 |
0 |
T157 |
18084 |
37 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
1991 |
0 |
0 |
T65 |
63808 |
67 |
0 |
0 |
T114 |
5905 |
1 |
0 |
0 |
T116 |
68927 |
88 |
0 |
0 |
T120 |
6885 |
1 |
0 |
0 |
T122 |
269334 |
687 |
0 |
0 |
T123 |
116470 |
730 |
0 |
0 |
T148 |
19343 |
46 |
0 |
0 |
T155 |
7298 |
11 |
0 |
0 |
T156 |
67116 |
84 |
0 |
0 |
T157 |
18084 |
21 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
2142 |
0 |
0 |
T65 |
63808 |
61 |
0 |
0 |
T114 |
5905 |
7 |
0 |
0 |
T116 |
68927 |
83 |
0 |
0 |
T120 |
6885 |
5 |
0 |
0 |
T122 |
269334 |
734 |
0 |
0 |
T123 |
116470 |
778 |
0 |
0 |
T148 |
19343 |
39 |
0 |
0 |
T155 |
7298 |
14 |
0 |
0 |
T156 |
67116 |
65 |
0 |
0 |
T157 |
18084 |
30 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
2618 |
0 |
0 |
T65 |
63808 |
159 |
0 |
0 |
T114 |
5905 |
9 |
0 |
0 |
T116 |
68927 |
268 |
0 |
0 |
T122 |
269334 |
646 |
0 |
0 |
T123 |
116470 |
779 |
0 |
0 |
T148 |
19343 |
45 |
0 |
0 |
T155 |
7298 |
23 |
0 |
0 |
T156 |
67116 |
153 |
0 |
0 |
T157 |
18084 |
13 |
0 |
0 |
T158 |
16176 |
54 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
2100 |
0 |
0 |
T65 |
63808 |
78 |
0 |
0 |
T114 |
5905 |
4 |
0 |
0 |
T116 |
68927 |
67 |
0 |
0 |
T120 |
6885 |
3 |
0 |
0 |
T122 |
269334 |
648 |
0 |
0 |
T123 |
116470 |
783 |
0 |
0 |
T148 |
19343 |
41 |
0 |
0 |
T155 |
7298 |
13 |
0 |
0 |
T156 |
67116 |
97 |
0 |
0 |
T157 |
18084 |
17 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
2952 |
0 |
0 |
T65 |
63808 |
193 |
0 |
0 |
T116 |
68927 |
252 |
0 |
0 |
T120 |
6885 |
26 |
0 |
0 |
T122 |
269334 |
675 |
0 |
0 |
T123 |
116470 |
798 |
0 |
0 |
T148 |
19343 |
65 |
0 |
0 |
T155 |
7298 |
5 |
0 |
0 |
T156 |
67116 |
270 |
0 |
0 |
T157 |
18084 |
38 |
0 |
0 |
T158 |
16176 |
59 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
2270 |
0 |
0 |
T65 |
63808 |
96 |
0 |
0 |
T114 |
5905 |
6 |
0 |
0 |
T116 |
68927 |
113 |
0 |
0 |
T120 |
6885 |
15 |
0 |
0 |
T122 |
269334 |
664 |
0 |
0 |
T123 |
116470 |
741 |
0 |
0 |
T148 |
19343 |
89 |
0 |
0 |
T155 |
7298 |
16 |
0 |
0 |
T156 |
67116 |
111 |
0 |
0 |
T157 |
18084 |
55 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
2038 |
0 |
0 |
T65 |
63808 |
59 |
0 |
0 |
T114 |
5905 |
2 |
0 |
0 |
T116 |
68927 |
72 |
0 |
0 |
T120 |
6885 |
10 |
0 |
0 |
T122 |
269334 |
653 |
0 |
0 |
T123 |
116470 |
702 |
0 |
0 |
T148 |
19343 |
65 |
0 |
0 |
T155 |
7298 |
14 |
0 |
0 |
T156 |
67116 |
73 |
0 |
0 |
T157 |
18084 |
52 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
2169 |
0 |
0 |
T65 |
63808 |
69 |
0 |
0 |
T116 |
68927 |
87 |
0 |
0 |
T120 |
6885 |
6 |
0 |
0 |
T122 |
269334 |
751 |
0 |
0 |
T123 |
116470 |
777 |
0 |
0 |
T148 |
19343 |
50 |
0 |
0 |
T155 |
7298 |
9 |
0 |
0 |
T156 |
67116 |
74 |
0 |
0 |
T157 |
18084 |
20 |
0 |
0 |
T158 |
16176 |
30 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
2059 |
0 |
0 |
T65 |
63808 |
86 |
0 |
0 |
T114 |
5905 |
10 |
0 |
0 |
T116 |
68927 |
71 |
0 |
0 |
T120 |
6885 |
6 |
0 |
0 |
T122 |
269334 |
660 |
0 |
0 |
T123 |
116470 |
670 |
0 |
0 |
T148 |
19343 |
75 |
0 |
0 |
T155 |
7298 |
5 |
0 |
0 |
T156 |
67116 |
72 |
0 |
0 |
T157 |
18084 |
46 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
2214 |
0 |
0 |
T65 |
63808 |
92 |
0 |
0 |
T114 |
5905 |
7 |
0 |
0 |
T116 |
68927 |
106 |
0 |
0 |
T120 |
6885 |
3 |
0 |
0 |
T122 |
269334 |
652 |
0 |
0 |
T123 |
116470 |
824 |
0 |
0 |
T148 |
19343 |
51 |
0 |
0 |
T155 |
7298 |
11 |
0 |
0 |
T156 |
67116 |
86 |
0 |
0 |
T157 |
18084 |
32 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
2233 |
0 |
0 |
T65 |
63808 |
96 |
0 |
0 |
T114 |
5905 |
8 |
0 |
0 |
T116 |
68927 |
98 |
0 |
0 |
T120 |
6885 |
7 |
0 |
0 |
T122 |
269334 |
687 |
0 |
0 |
T123 |
116470 |
802 |
0 |
0 |
T148 |
19343 |
70 |
0 |
0 |
T155 |
7298 |
15 |
0 |
0 |
T156 |
67116 |
67 |
0 |
0 |
T157 |
18084 |
32 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
460028901 |
2177 |
0 |
0 |
T65 |
63808 |
40 |
0 |
0 |
T116 |
68927 |
90 |
0 |
0 |
T120 |
6885 |
3 |
0 |
0 |
T122 |
269334 |
687 |
0 |
0 |
T123 |
116470 |
777 |
0 |
0 |
T148 |
19343 |
65 |
0 |
0 |
T155 |
7298 |
10 |
0 |
0 |
T156 |
67116 |
88 |
0 |
0 |
T157 |
18084 |
37 |
0 |
0 |
T158 |
16176 |
11 |
0 |
0 |