Group : spi_device_env_pkg::tpm_read_hw_reg_cg_wrap::tpm_read_hw_reg_cg
Group Instance : tpm_access_0
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_access_0
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_access_0
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : tpm_access_1
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_access_1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_access_1
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : tpm_access_2
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_access_2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_access_2
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : tpm_access_3
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_access_3
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_access_3
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : tpm_access_4
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_access_4
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_access_4
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : tpm_did_vid
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_did_vid
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_did_vid
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : tpm_hash_start
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_hash_start
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_hash_start
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : tpm_int_enable
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_int_enable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_int_enable
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : tpm_int_status
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_int_status
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_int_status
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : tpm_int_vector
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_int_vector
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_int_vector
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : tpm_intf_capability
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_intf_capability
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_intf_capability
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : tpm_rid
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_rid
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_rid
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : tpm_sts
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_sts
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_sts
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_hit
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| done |
511 |
1 |
|
|
T3 |
6 |
|
T14 |
16 |
|
T24 |
2 |
Summary for Variable cp_hit
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| done |
504 |
1 |
|
|
T3 |
6 |
|
T4 |
4 |
|
T14 |
20 |
Summary for Variable cp_hit
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| done |
546 |
1 |
|
|
T3 |
6 |
|
T14 |
18 |
|
T37 |
2 |
Summary for Variable cp_hit
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| done |
522 |
1 |
|
|
T3 |
12 |
|
T4 |
2 |
|
T10 |
2 |
Summary for Variable cp_hit
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| done |
500 |
1 |
|
|
T3 |
2 |
|
T4 |
2 |
|
T14 |
20 |
Summary for Variable cp_hit
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| done |
2536 |
1 |
|
|
T3 |
42 |
|
T4 |
10 |
|
T10 |
16 |
Summary for Variable cp_hit
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| done |
2480 |
1 |
|
|
T3 |
48 |
|
T4 |
10 |
|
T10 |
10 |
Summary for Variable cp_hit
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| done |
2522 |
1 |
|
|
T3 |
46 |
|
T4 |
6 |
|
T10 |
10 |
Summary for Variable cp_hit
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| done |
2450 |
1 |
|
|
T3 |
40 |
|
T4 |
2 |
|
T10 |
10 |
Summary for Variable cp_hit
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| done |
2648 |
1 |
|
|
T3 |
50 |
|
T4 |
8 |
|
T10 |
12 |
Summary for Variable cp_hit
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| done |
6 |
1 |
|
|
T26 |
2 |
|
T188 |
2 |
|
T286 |
2 |
Summary for Variable cp_hit
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| done |
2574 |
1 |
|
|
T3 |
38 |
|
T4 |
6 |
|
T10 |
10 |
Summary for Variable cp_hit
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| done |
2184 |
1 |
|
|
T3 |
29 |
|
T4 |
8 |
|
T7 |
2 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |