Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4020749	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4525672

1

T1

1

T3

482

T4

3133

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4662360	1			T1	1		T2	49		T3	1
values[0x0]	1941772	1			T3	290		T4	1548		T5	1766
values[0x1]	1942289	1			T3	293		T4	1405		T5	1766

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2829402	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5717019

1

T1

1

T2

15

T3

508

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	32848	1			T5	12		T6	1		T8	49
valid_sources[0x01]	35839	1			T3	1		T5	16		T6	4
valid_sources[0x02]	41291	1			T4	599		T5	21		T6	1
valid_sources[0x03]	32245	1			T3	1		T5	37		T8	42
valid_sources[0x04]	32730	1			T2	1		T3	1		T5	14
valid_sources[0x05]	35976	1			T3	3		T5	4		T6	5
valid_sources[0x06]	32804	1			T3	1		T5	6		T8	5
valid_sources[0x07]	31260	1			T3	4		T5	16		T6	1
valid_sources[0x08]	33051	1			T3	13		T4	45		T5	25
valid_sources[0x09]	30431	1			T3	4		T5	19		T6	3
valid_sources[0x0a]	33031	1			T3	2		T4	1		T5	15
valid_sources[0x0b]	33151	1			T2	2		T3	4		T5	5
valid_sources[0x0c]	31153	1			T3	6		T4	1		T5	11
valid_sources[0x0d]	35154	1			T5	11		T6	10		T8	53
valid_sources[0x0e]	33668	1			T3	5		T5	40		T6	4
valid_sources[0x0f]	37711	1			T3	2		T4	1		T5	16
valid_sources[0x10]	31904	1			T2	1		T5	48		T6	4
valid_sources[0x11]	31449	1			T5	14		T8	35		T10	180
valid_sources[0x12]	33031	1			T4	464		T5	12		T6	2
valid_sources[0x13]	30325	1			T2	2		T3	2		T5	6
valid_sources[0x14]	30816	1			T2	2		T5	17		T8	45
valid_sources[0x15]	35374	1			T2	1		T6	1		T8	28
valid_sources[0x16]	31252	1			T5	21		T8	35		T10	163
valid_sources[0x17]	37257	1			T3	1		T5	10		T8	38
valid_sources[0x18]	31407	1			T3	4		T5	21		T8	16
valid_sources[0x19]	32512	1			T3	1		T5	48		T6	2
valid_sources[0x1a]	31824	1			T3	2		T4	6		T5	7
valid_sources[0x1b]	33943	1			T3	7		T5	8		T6	1
valid_sources[0x1c]	33328	1			T3	8		T5	4		T6	1
valid_sources[0x1d]	34306	1			T5	11		T6	8		T8	41
valid_sources[0x1e]	36603	1			T5	9		T6	5		T8	70
valid_sources[0x1f]	36195	1			T5	35		T8	44		T10	164
valid_sources[0x20]	34021	1			T3	1		T5	44		T7	7
valid_sources[0x21]	34331	1			T5	18		T8	44		T10	175
valid_sources[0x22]	40360	1			T3	1		T5	16		T6	1
valid_sources[0x23]	33104	1			T3	11		T4	3		T5	21
valid_sources[0x24]	34035	1			T3	1		T5	10		T8	44
valid_sources[0x25]	31008	1			T3	1		T5	5		T8	108
valid_sources[0x26]	31481	1			T5	6		T6	1		T8	53
valid_sources[0x27]	30914	1			T3	2		T5	15		T6	2
valid_sources[0x28]	33376	1			T3	1		T5	18		T6	7
valid_sources[0x29]	32540	1			T2	3		T5	11		T6	7
valid_sources[0x2a]	32900	1			T2	3		T3	2		T5	12
valid_sources[0x2b]	30252	1			T3	3		T4	2		T5	15
valid_sources[0x2c]	32079	1			T5	9		T7	2		T8	47
valid_sources[0x2d]	31337	1			T5	13		T8	28		T10	168
valid_sources[0x2e]	29559	1			T4	1		T5	23		T6	1
valid_sources[0x2f]	32711	1			T3	8		T4	4		T5	8
valid_sources[0x30]	34273	1			T3	2		T5	14		T8	24
valid_sources[0x31]	33282	1			T5	20		T6	4		T7	1
valid_sources[0x32]	39839	1			T3	11		T5	10		T8	44
valid_sources[0x33]	29432	1			T3	1		T4	185		T5	28
valid_sources[0x34]	32035	1			T3	1		T4	319		T5	8
valid_sources[0x35]	31112	1			T3	2		T4	173		T5	29
valid_sources[0x36]	32499	1			T3	1		T4	71		T8	55
valid_sources[0x37]	32003	1			T5	11		T6	1		T8	39
valid_sources[0x38]	30868	1			T3	2		T5	5		T6	6
valid_sources[0x39]	29135	1			T3	1		T5	15		T6	10
valid_sources[0x3a]	36548	1			T3	3		T5	14		T6	15
valid_sources[0x3b]	32505	1			T3	6		T5	14		T6	4
valid_sources[0x3c]	32278	1			T3	4		T5	7		T6	4
valid_sources[0x3d]	34843	1			T3	2		T4	2		T5	20
valid_sources[0x3e]	33129	1			T5	15		T6	9		T8	86
valid_sources[0x3f]	33931	1			T3	9		T4	63		T5	20
valid_sources[0x40]	40636	1			T5	1		T6	9		T8	65
valid_sources[0x41]	39047	1			T5	13		T6	11		T8	39
valid_sources[0x42]	32026	1			T3	5		T5	9		T6	12
valid_sources[0x43]	32637	1			T5	22		T8	70		T10	188
valid_sources[0x44]	32486	1			T3	1		T4	2		T5	8
valid_sources[0x45]	32625	1			T3	2		T4	2		T5	14
valid_sources[0x46]	31985	1			T3	1		T4	1		T5	26
valid_sources[0x47]	34740	1			T3	1		T4	1		T5	19
valid_sources[0x48]	34547	1			T3	3		T5	12		T8	49
valid_sources[0x49]	35998	1			T3	1		T5	15		T8	55
valid_sources[0x4a]	29927	1			T3	2		T5	1		T8	80
valid_sources[0x4b]	51312	1			T3	1		T5	24		T8	69
valid_sources[0x4c]	32628	1			T3	5		T5	9		T6	1
valid_sources[0x4d]	46533	1			T3	1		T5	14		T6	3
valid_sources[0x4e]	36038	1			T3	3		T5	15		T6	10
valid_sources[0x4f]	30938	1			T5	20		T6	9		T8	43
valid_sources[0x50]	32217	1			T3	7		T5	13		T6	11
valid_sources[0x51]	30536	1			T2	1		T3	2		T4	2
valid_sources[0x52]	39530	1			T5	12		T8	23		T10	194
valid_sources[0x53]	36771	1			T2	1		T3	2		T5	14
valid_sources[0x54]	35787	1			T3	2		T5	3		T6	1
valid_sources[0x55]	37368	1			T3	2		T5	16		T6	1
valid_sources[0x56]	35753	1			T5	11		T6	17		T8	44
valid_sources[0x57]	28223	1			T3	1		T5	25		T6	4
valid_sources[0x58]	29820	1			T3	3		T4	21		T5	11
valid_sources[0x59]	30336	1			T3	2		T5	26		T8	46
valid_sources[0x5a]	31126	1			T3	2		T4	2		T5	13
valid_sources[0x5b]	35107	1			T5	13		T6	7		T8	25
valid_sources[0x5c]	32591	1			T3	1		T5	14		T6	1
valid_sources[0x5d]	30156	1			T4	3		T5	5		T8	31
valid_sources[0x5e]	33178	1			T3	1		T5	25		T8	33
valid_sources[0x5f]	31352	1			T3	5		T5	21		T6	2
valid_sources[0x60]	36857	1			T3	1		T5	19		T8	34
valid_sources[0x61]	32915	1			T4	133		T5	22		T8	47
valid_sources[0x62]	33421	1			T2	1		T5	31		T6	1
valid_sources[0x63]	33252	1			T3	6		T5	8		T6	5
valid_sources[0x64]	32638	1			T3	9		T4	2		T5	29
valid_sources[0x65]	40805	1			T5	42		T8	21		T10	167
valid_sources[0x66]	33771	1			T3	1		T5	16		T8	28
valid_sources[0x67]	31617	1			T5	8		T8	23		T10	181
valid_sources[0x68]	31214	1			T5	5		T8	53		T10	164
valid_sources[0x69]	33353	1			T3	2		T4	1		T5	5
valid_sources[0x6a]	34088	1			T2	5		T5	29		T8	42
valid_sources[0x6b]	28991	1			T3	2		T4	91		T5	29
valid_sources[0x6c]	35218	1			T3	1		T5	32		T6	6
valid_sources[0x6d]	35280	1			T5	21		T6	1		T8	33
valid_sources[0x6e]	30399	1			T3	3		T5	19		T6	2
valid_sources[0x6f]	31682	1			T2	2		T3	3		T5	13
valid_sources[0x70]	33070	1			T3	4		T4	55		T5	9
valid_sources[0x71]	29782	1			T3	4		T5	8		T6	4
valid_sources[0x72]	32357	1			T2	2		T3	6		T4	1
valid_sources[0x73]	42151	1			T3	2		T5	13		T6	5
valid_sources[0x74]	32590	1			T3	2		T4	31		T5	23
valid_sources[0x75]	28930	1			T2	1		T3	3		T5	26
valid_sources[0x76]	32141	1			T3	6		T5	11		T6	2
valid_sources[0x77]	34570	1			T1	1		T3	2		T5	20
valid_sources[0x78]	38632	1			T3	2		T5	19		T8	36
valid_sources[0x79]	33019	1			T5	11		T6	2		T8	40
valid_sources[0x7a]	30214	1			T5	8		T6	3		T8	58
valid_sources[0x7b]	32741	1			T3	2		T5	11		T6	6
valid_sources[0x7c]	32165	1			T5	12		T6	7		T8	34
valid_sources[0x7d]	33872	1			T3	2		T5	10		T6	3
valid_sources[0x7e]	31055	1			T5	31		T6	8		T8	68
valid_sources[0x7f]	33303	1			T3	10		T5	9		T8	50
valid_sources[0x80]	31506	1			T3	1		T4	69		T5	19

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1014603

1

T1

1

T4

890

T5

344

values[0x0]

all_enables

biggest_size

1768251

1

T3

240

T4

1209

T5

1760

values[0x1]

all_enables

biggest_size

1742818

1

T3

242

T4

1034

T5

1747