Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

4041446

1

T2

49

T3

102

T4

2539

full_word

4526818

1

T1

1

T3

482

T4

3133

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8567904	1			T1	1		T2	49		T3	584
auto[TlIntgErrCmd]	121	1			T62	6		T64	12		T83	12
auto[TlIntgErrData]	110	1			T62	7		T64	9		T83	10
auto[TlIntgErrBoth]	129	1			T62	7		T64	9		T83	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4665685

1

T1

1

T2

49

T3

1

auto[1]

3902579

1

T3

583

T4

2953

T5

3532

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3650680	1			T2	49		T3	1		T4	1829
auto[TlIntgErrNone]	partial	auto[1]	390438	1			T3	101		T4	710		T5	25
auto[TlIntgErrNone]	full_word	auto[0]	1014842	1			T1	1		T4	890		T5	344
auto[TlIntgErrNone]	full_word	auto[1]	3511944	1			T3	482		T4	2243		T5	3507
auto[TlIntgErrCmd]	partial	auto[0]	50	1			T62	4		T64	4		T83	4
auto[TlIntgErrCmd]	partial	auto[1]	62	1			T62	2		T64	5		T83	7
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T64	1		T145	1		T146	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T64	2		T83	1		T145	1
auto[TlIntgErrData]	partial	auto[0]	45	1			T62	3		T64	5		T83	3
auto[TlIntgErrData]	partial	auto[1]	56	1			T62	3		T64	3		T83	7
auto[TlIntgErrData]	full_word	auto[0]	3	1			T62	1		T147	1		T148	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T64	1		T149	1		T150	1
auto[TlIntgErrBoth]	partial	auto[0]	55	1			T62	3		T64	5		T83	3
auto[TlIntgErrBoth]	partial	auto[1]	60	1			T62	2		T64	3		T83	5
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T62	2		T149	1		T151	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T64	1		T142	1		T143	1