Unified Coverage Report :: Module :: prim_generic_ram_1r1w

Module : prim_generic_ram_1r1w

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1r1w

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	632678854	3449636	0	0
gen_wmask[1].MaskCheckPortA_A	632678854	3449636	0	0
gen_wmask[2].MaskCheckPortA_A	632678854	3449636	0	0
gen_wmask[3].MaskCheckPortA_A	632678854	3449636	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	632678854	3449636	0	0
T4	473817	4264	0	0
T5	414488	6628	0	0
T6	10270	832	0	0
T7	2856	0	0	0
T8	985679	10400	0	0
T9	8598	142	0	0
T10	669557	15584	0	0
T11	2238	0	0	0
T12	6598	74	0	0
T13	345574	832	0	0
T14	98936	0	0	0
T15	20383	832	0	0
T20	0	4	0	0
T23	0	97	0	0
T24	0	1372	0	0
T25	0	107	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	632678854	3449636	0	0
T4	473817	4264	0	0
T5	414488	6628	0	0
T6	10270	832	0	0
T7	2856	0	0	0
T8	985679	10400	0	0
T9	8598	142	0	0
T10	669557	15584	0	0
T11	2238	0	0	0
T12	6598	74	0	0
T13	345574	832	0	0
T14	98936	0	0	0
T15	20383	832	0	0
T20	0	4	0	0
T23	0	97	0	0
T24	0	1372	0	0
T25	0	107	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	632678854	3449636	0	0
T4	473817	4264	0	0
T5	414488	6628	0	0
T6	10270	832	0	0
T7	2856	0	0	0
T8	985679	10400	0	0
T9	8598	142	0	0
T10	669557	15584	0	0
T11	2238	0	0	0
T12	6598	74	0	0
T13	345574	832	0	0
T14	98936	0	0	0
T15	20383	832	0	0
T20	0	4	0	0
T23	0	97	0	0
T24	0	1372	0	0
T25	0	107	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	632678854	3449636	0	0
T4	473817	4264	0	0
T5	414488	6628	0	0
T6	10270	832	0	0
T7	2856	0	0	0
T8	985679	10400	0	0
T9	8598	142	0	0
T10	669557	15584	0	0
T11	2238	0	0	0
T12	6598	74	0	0
T13	345574	832	0	0
T14	98936	0	0	0
T15	20383	832	0	0
T20	0	4	0	0
T23	0	97	0	0
T24	0	1372	0	0
T25	0	107	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			==> MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T8
0	Covered	T3,T4,T5

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	477549891	2203795	0	0
gen_wmask[1].MaskCheckPortA_A	477549891	2203795	0	0
gen_wmask[2].MaskCheckPortA_A	477549891	2203795	0	0
gen_wmask[3].MaskCheckPortA_A	477549891	2203795	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477549891	2203795	0	0
T4	132503	1494	0	0
T5	173184	3328	0	0
T6	10270	832	0	0
T7	2280	0	0	0
T8	168236	8320	0	0
T9	6824	7	0	0
T10	190935	8073	0	0
T11	2238	0	0	0
T12	5766	2	0	0
T13	177478	832	0	0
T15	0	832	0	0
T23	0	28	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477549891	2203795	0	0
T4	132503	1494	0	0
T5	173184	3328	0	0
T6	10270	832	0	0
T7	2280	0	0	0
T8	168236	8320	0	0
T9	6824	7	0	0
T10	190935	8073	0	0
T11	2238	0	0	0
T12	5766	2	0	0
T13	177478	832	0	0
T15	0	832	0	0
T23	0	28	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477549891	2203795	0	0
T4	132503	1494	0	0
T5	173184	3328	0	0
T6	10270	832	0	0
T7	2280	0	0	0
T8	168236	8320	0	0
T9	6824	7	0	0
T10	190935	8073	0	0
T11	2238	0	0	0
T12	5766	2	0	0
T13	177478	832	0	0
T15	0	832	0	0
T23	0	28	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477549891	2203795	0	0
T4	132503	1494	0	0
T5	173184	3328	0	0
T6	10270	832	0	0
T7	2280	0	0	0
T8	168236	8320	0	0
T9	6824	7	0	0
T10	190935	8073	0	0
T11	2238	0	0	0
T12	5766	2	0	0
T13	177478	832	0	0
T15	0	832	0	0
T23	0	28	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T8
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	155128963	1245841	0	0
gen_wmask[1].MaskCheckPortA_A	155128963	1245841	0	0
gen_wmask[2].MaskCheckPortA_A	155128963	1245841	0	0
gen_wmask[3].MaskCheckPortA_A	155128963	1245841	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155128963	1245841	0	0
T4	341314	2770	0	0
T5	241304	3300	0	0
T7	576	0	0	0
T8	817443	2080	0	0
T9	1774	135	0	0
T10	478622	7511	0	0
T12	832	72	0	0
T13	168096	0	0	0
T14	98936	0	0	0
T15	20383	0	0	0
T20	0	4	0	0
T23	0	69	0	0
T24	0	1372	0	0
T25	0	107	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155128963	1245841	0	0
T4	341314	2770	0	0
T5	241304	3300	0	0
T7	576	0	0	0
T8	817443	2080	0	0
T9	1774	135	0	0
T10	478622	7511	0	0
T12	832	72	0	0
T13	168096	0	0	0
T14	98936	0	0	0
T15	20383	0	0	0
T20	0	4	0	0
T23	0	69	0	0
T24	0	1372	0	0
T25	0	107	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155128963	1245841	0	0
T4	341314	2770	0	0
T5	241304	3300	0	0
T7	576	0	0	0
T8	817443	2080	0	0
T9	1774	135	0	0
T10	478622	7511	0	0
T12	832	72	0	0
T13	168096	0	0	0
T14	98936	0	0	0
T15	20383	0	0	0
T20	0	4	0	0
T23	0	69	0	0
T24	0	1372	0	0
T25	0	107	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155128963	1245841	0	0
T4	341314	2770	0	0
T5	241304	3300	0	0
T7	576	0	0	0
T8	817443	2080	0	0
T9	1774	135	0	0
T10	478622	7511	0	0
T12	832	72	0	0
T13	168096	0	0	0
T14	98936	0	0	0
T15	20383	0	0	0
T20	0	4	0	0
T23	0	69	0	0
T24	0	1372	0	0
T25	0	107	0	0