Unified Coverage Report :: Module :: prim_pulse_sync

Module : prim_pulse_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_readbuf_watermark_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_flash_readbuf_flip_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_upload.u_payloadptr_clr_psync	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_upload.u_payloadptr_clr_psync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.37	100.00	86.11		100.00	95.74	100.00	u_upload

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T5,T8,T10
1	0	Covered	T5,T8,T10
1	1	Covered	T5,T8,T10

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T10
1	0	Covered	T5,T8,T10
1	1	Covered	T5,T8,T10

---

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1432649673	2848	0	0
SrcPulseCheck_M	465386889	2848	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1432649673	2848	0	0
T5	173184	6	0	0
T6	10270	0	0	0
T7	2280	0	0	0
T8	168236	8	0	0
T9	6824	0	0	0
T10	190935	11	0	0
T11	2238	0	0	0
T12	5766	0	0	0
T13	177478	0	0	0
T14	128548	0	0	0
T15	251914	7	0	0
T16	917312	0	0	0
T17	62210	0	0	0
T18	274362	7	0	0
T19	151550	0	0	0
T20	175290	2	0	0
T23	17584	0	0	0
T24	542772	0	0	0
T26	0	13	0	0
T36	0	4	0	0
T37	0	22	0	0
T39	0	7	0	0
T40	0	10	0	0
T42	0	6	0	0
T58	3088	0	0	0
T117	5602	0	0	0
T118	0	7	0	0
T119	0	6	0	0
T120	0	7	0	0
T121	0	7	0	0
T122	0	1	0	0
T123	0	7	0	0
T124	0	1	0	0
T125	0	5	0	0
T126	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	465386889	2848	0	0
T5	241304	6	0	0
T7	576	0	0	0
T8	817443	8	0	0
T9	1774	0	0	0
T10	478622	11	0	0
T12	832	0	0	0
T13	168096	0	0	0
T14	98936	0	0	0
T15	61149	7	0	0
T16	148896	0	0	0
T17	54880	0	0	0
T18	38180	7	0	0
T19	431002	0	0	0
T20	324932	2	0	0
T23	5544	0	0	0
T24	83444	0	0	0
T25	6916	0	0	0
T26	0	13	0	0
T36	0	4	0	0
T37	0	22	0	0
T39	0	7	0	0
T40	0	10	0	0
T41	265122	0	0	0
T42	0	6	0	0
T118	0	7	0	0
T119	0	6	0	0
T120	0	7	0	0
T121	0	7	0	0
T122	0	1	0	0
T123	0	7	0	0
T124	0	1	0	0
T125	0	5	0	0
T126	0	5	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T15,T18,T39
1	0	Covered	T15,T18,T39
1	1	Covered	T15,T18,T39

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T18,T39
1	0	Covered	T15,T18,T39
1	1	Covered	T15,T18,T39

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	477549891	168	0	0
SrcPulseCheck_M	155128963	168	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477549891	168	0	0
T15	125957	2	0	0
T16	458656	0	0	0
T17	31105	0	0	0
T18	137181	2	0	0
T19	75775	0	0	0
T20	87645	0	0	0
T23	8792	0	0	0
T24	271386	0	0	0
T39	0	2	0	0
T58	1544	0	0	0
T117	2801	0	0	0
T118	0	2	0	0
T119	0	3	0	0
T120	0	2	0	0
T121	0	2	0	0
T122	0	1	0	0
T123	0	2	0	0
T124	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	155128963	168	0	0
T15	20383	2	0	0
T16	74448	0	0	0
T17	27440	0	0	0
T18	19090	2	0	0
T19	215501	0	0	0
T20	162466	0	0	0
T23	1848	0	0	0
T24	41722	0	0	0
T25	3458	0	0	0
T39	0	2	0	0
T41	132561	0	0	0
T118	0	2	0	0
T119	0	3	0	0
T120	0	2	0	0
T121	0	2	0	0
T122	0	1	0	0
T123	0	2	0	0
T124	0	1	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T15,T18,T39
1	0	Covered	T15,T18,T39
1	1	Covered	T15,T18,T39

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T18,T39
1	0	Covered	T15,T18,T39
1	1	Covered	T15,T18,T39

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	477549891	307	0	0
SrcPulseCheck_M	155128963	307	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477549891	307	0	0
T15	125957	5	0	0
T16	458656	0	0	0
T17	31105	0	0	0
T18	137181	5	0	0
T19	75775	0	0	0
T20	87645	0	0	0
T23	8792	0	0	0
T24	271386	0	0	0
T39	0	5	0	0
T58	1544	0	0	0
T117	2801	0	0	0
T118	0	5	0	0
T119	0	3	0	0
T120	0	5	0	0
T121	0	5	0	0
T123	0	5	0	0
T125	0	5	0	0
T126	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	155128963	307	0	0
T15	20383	5	0	0
T16	74448	0	0	0
T17	27440	0	0	0
T18	19090	5	0	0
T19	215501	0	0	0
T20	162466	0	0	0
T23	1848	0	0	0
T24	41722	0	0	0
T25	3458	0	0	0
T39	0	5	0	0
T41	132561	0	0	0
T118	0	5	0	0
T119	0	3	0	0
T120	0	5	0	0
T121	0	5	0	0
T123	0	5	0	0
T125	0	5	0	0
T126	0	5	0	0

Line Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T5,T8,T10
1	0	Covered	T5,T8,T10
1	1	Covered	T5,T8,T10

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T10
1	0	Covered	T5,T8,T10
1	1	Covered	T5,T8,T10

---

Branch Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	477549891	2373	0	0
SrcPulseCheck_M	155128963	2373	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477549891	2373	0	0
T5	173184	6	0	0
T6	10270	0	0	0
T7	2280	0	0	0
T8	168236	8	0	0
T9	6824	0	0	0
T10	190935	11	0	0
T11	2238	0	0	0
T12	5766	0	0	0
T13	177478	0	0	0
T14	128548	0	0	0
T20	0	2	0	0
T26	0	13	0	0
T36	0	4	0	0
T37	0	22	0	0
T40	0	10	0	0
T42	0	6	0	0
T43	0	11	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	155128963	2373	0	0
T5	241304	6	0	0
T7	576	0	0	0
T8	817443	8	0	0
T9	1774	0	0	0
T10	478622	11	0	0
T12	832	0	0	0
T13	168096	0	0	0
T14	98936	0	0	0
T15	20383	0	0	0
T20	0	2	0	0
T23	1848	0	0	0
T26	0	13	0	0
T36	0	4	0	0
T37	0	22	0	0
T40	0	10	0	0
T42	0	6	0	0
T43	0	11	0	0