Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	480072078	3010422	0	0
DepthKnown_A	480072078	479944168	0	0
RvalidKnown_A	480072078	479944168	0	0
WreadyKnown_A	480072078	479944168	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480072078	3010422	0	0
T5	173184	4994	0	0
T6	10270	832	0	0
T7	2280	0	0	0
T8	168236	13306	0	0
T9	6824	0	0	0
T10	190935	9149	0	0
T11	2238	0	0	0
T12	5766	0	0	0
T13	177478	832	0	0
T14	128548	0	0	0
T15	0	1663	0	0
T16	0	832	0	0
T17	0	832	0	0
T18	0	1663	0	0
T19	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480072078	479944168	0	0
T1	3155	2227	0	0
T2	1564	1505	0	0
T3	354707	354634	0	0
T4	132503	132449	0	0
T5	173184	173094	0	0
T6	10270	10196	0	0
T7	2280	2206	0	0
T8	168236	168231	0	0
T9	6824	6769	0	0
T10	190935	190925	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480072078	479944168	0	0
T1	3155	2227	0	0
T2	1564	1505	0	0
T3	354707	354634	0	0
T4	132503	132449	0	0
T5	173184	173094	0	0
T6	10270	10196	0	0
T7	2280	2206	0	0
T8	168236	168231	0	0
T9	6824	6769	0	0
T10	190935	190925	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480072078	479944168	0	0
T1	3155	2227	0	0
T2	1564	1505	0	0
T3	354707	354634	0	0
T4	132503	132449	0	0
T5	173184	173094	0	0
T6	10270	10196	0	0
T7	2280	2206	0	0
T8	168236	168231	0	0
T9	6824	6769	0	0
T10	190935	190925	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	480072078	3513525	0	0
DepthKnown_A	480072078	479944168	0	0
RvalidKnown_A	480072078	479944168	0	0
WreadyKnown_A	480072078	479944168	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480072078	3513525	0	0
T5	173184	9047	0	0
T6	10270	3695	0	0
T7	2280	0	0	0
T8	168236	8320	0	0
T9	6824	0	0	0
T10	190935	6656	0	0
T11	2238	0	0	0
T12	5766	0	0	0
T13	177478	2646	0	0
T14	128548	0	0	0
T15	0	832	0	0
T16	0	2592	0	0
T17	0	832	0	0
T18	0	832	0	0
T19	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480072078	479944168	0	0
T1	3155	2227	0	0
T2	1564	1505	0	0
T3	354707	354634	0	0
T4	132503	132449	0	0
T5	173184	173094	0	0
T6	10270	10196	0	0
T7	2280	2206	0	0
T8	168236	168231	0	0
T9	6824	6769	0	0
T10	190935	190925	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480072078	479944168	0	0
T1	3155	2227	0	0
T2	1564	1505	0	0
T3	354707	354634	0	0
T4	132503	132449	0	0
T5	173184	173094	0	0
T6	10270	10196	0	0
T7	2280	2206	0	0
T8	168236	168231	0	0
T9	6824	6769	0	0
T10	190935	190925	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480072078	479944168	0	0
T1	3155	2227	0	0
T2	1564	1505	0	0
T3	354707	354634	0	0
T4	132503	132449	0	0
T5	173184	173094	0	0
T6	10270	10196	0	0
T7	2280	2206	0	0
T8	168236	168231	0	0
T9	6824	6769	0	0
T10	190935	190925	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	480072078	189913	0	0
DepthKnown_A	480072078	479944168	0	0
RvalidKnown_A	480072078	479944168	0	0
WreadyKnown_A	480072078	479944168	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480072078	189913	0	0
T4	132503	721	0	0
T5	173184	192	0	0
T6	10270	0	0	0
T7	2280	0	0	0
T8	168236	64	0	0
T9	6824	35	0	0
T10	190935	1490	0	0
T11	2238	0	0	0
T12	5766	18	0	0
T13	177478	0	0	0
T23	0	18	0	0
T24	0	353	0	0
T25	0	27	0	0
T37	0	977	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480072078	479944168	0	0
T1	3155	2227	0	0
T2	1564	1505	0	0
T3	354707	354634	0	0
T4	132503	132449	0	0
T5	173184	173094	0	0
T6	10270	10196	0	0
T7	2280	2206	0	0
T8	168236	168231	0	0
T9	6824	6769	0	0
T10	190935	190925	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480072078	479944168	0	0
T1	3155	2227	0	0
T2	1564	1505	0	0
T3	354707	354634	0	0
T4	132503	132449	0	0
T5	173184	173094	0	0
T6	10270	10196	0	0
T7	2280	2206	0	0
T8	168236	168231	0	0
T9	6824	6769	0	0
T10	190935	190925	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480072078	479944168	0	0
T1	3155	2227	0	0
T2	1564	1505	0	0
T3	354707	354634	0	0
T4	132503	132449	0	0
T5	173184	173094	0	0
T6	10270	10196	0	0
T7	2280	2206	0	0
T8	168236	168231	0	0
T9	6824	6769	0	0
T10	190935	190925	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	480072078	459459	0	0
DepthKnown_A	480072078	479944168	0	0
RvalidKnown_A	480072078	479944168	0	0
WreadyKnown_A	480072078	479944168	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480072078	459459	0	0
T4	132503	721	0	0
T5	173184	898	0	0
T6	10270	0	0	0
T7	2280	0	0	0
T8	168236	64	0	0
T9	6824	35	0	0
T10	190935	1489	0	0
T11	2238	0	0	0
T12	5766	18	0	0
T13	177478	0	0	0
T23	0	18	0	0
T24	0	353	0	0
T25	0	27	0	0
T37	0	977	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480072078	479944168	0	0
T1	3155	2227	0	0
T2	1564	1505	0	0
T3	354707	354634	0	0
T4	132503	132449	0	0
T5	173184	173094	0	0
T6	10270	10196	0	0
T7	2280	2206	0	0
T8	168236	168231	0	0
T9	6824	6769	0	0
T10	190935	190925	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480072078	479944168	0	0
T1	3155	2227	0	0
T2	1564	1505	0	0
T3	354707	354634	0	0
T4	132503	132449	0	0
T5	173184	173094	0	0
T6	10270	10196	0	0
T7	2280	2206	0	0
T8	168236	168231	0	0
T9	6824	6769	0	0
T10	190935	190925	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480072078	479944168	0	0
T1	3155	2227	0	0
T2	1564	1505	0	0
T3	354707	354634	0	0
T4	132503	132449	0	0
T5	173184	173094	0	0
T6	10270	10196	0	0
T7	2280	2206	0	0
T8	168236	168231	0	0
T9	6824	6769	0	0
T10	190935	190925	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	480072078	6791663	0	0
DepthKnown_A	480072078	479944168	0	0
RvalidKnown_A	480072078	479944168	0	0
WreadyKnown_A	480072078	479944168	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480072078	6791663	0	0
T1	3155	1	0	0
T2	1564	49	0	0
T3	354707	584	0	0
T4	132503	4971	0	0
T5	173184	552	0	0
T6	10270	45	0	0
T7	2280	26	0	0
T8	168236	3064	0	0
T9	6824	691	0	0
T10	190935	36090	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480072078	479944168	0	0
T1	3155	2227	0	0
T2	1564	1505	0	0
T3	354707	354634	0	0
T4	132503	132449	0	0
T5	173184	173094	0	0
T6	10270	10196	0	0
T7	2280	2206	0	0
T8	168236	168231	0	0
T9	6824	6769	0	0
T10	190935	190925	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480072078	479944168	0	0
T1	3155	2227	0	0
T2	1564	1505	0	0
T3	354707	354634	0	0
T4	132503	132449	0	0
T5	173184	173094	0	0
T6	10270	10196	0	0
T7	2280	2206	0	0
T8	168236	168231	0	0
T9	6824	6769	0	0
T10	190935	190925	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480072078	479944168	0	0
T1	3155	2227	0	0
T2	1564	1505	0	0
T3	354707	354634	0	0
T4	132503	132449	0	0
T5	173184	173094	0	0
T6	10270	10196	0	0
T7	2280	2206	0	0
T8	168236	168231	0	0
T9	6824	6769	0	0
T10	190935	190925	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	480072078	13995335	0	0
DepthKnown_A	480072078	479944168	0	0
RvalidKnown_A	480072078	479944168	0	0
WreadyKnown_A	480072078	479944168	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480072078	13995335	0	0
T1	3155	1	0	0
T2	1564	216	0	0
T3	354707	584	0	0
T4	132503	4951	0	0
T5	173184	2411	0	0
T6	10270	196	0	0
T7	2280	26	0	0
T8	168236	3060	0	0
T9	6824	691	0	0
T10	190935	35894	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480072078	479944168	0	0
T1	3155	2227	0	0
T2	1564	1505	0	0
T3	354707	354634	0	0
T4	132503	132449	0	0
T5	173184	173094	0	0
T6	10270	10196	0	0
T7	2280	2206	0	0
T8	168236	168231	0	0
T9	6824	6769	0	0
T10	190935	190925	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480072078	479944168	0	0
T1	3155	2227	0	0
T2	1564	1505	0	0
T3	354707	354634	0	0
T4	132503	132449	0	0
T5	173184	173094	0	0
T6	10270	10196	0	0
T7	2280	2206	0	0
T8	168236	168231	0	0
T9	6824	6769	0	0
T10	190935	190925	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480072078	479944168	0	0
T1	3155	2227	0	0
T2	1564	1505	0	0
T3	354707	354634	0	0
T4	132503	132449	0	0
T5	173184	173094	0	0
T6	10270	10196	0	0
T7	2280	2206	0	0
T8	168236	168231	0	0
T9	6824	6769	0	0
T10	190935	190925	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0