Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T9,T10
1	0	Covered	T4,T9,T10

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T7
1	0	Unreachable
1	1	Covered	T4,T9,T10

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T8,T10

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T10
1	0	Covered	T5,T8,T10

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T10
1	0	Unreachable
1	1	Covered	T5,T8,T10

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T8
1	0	Covered	T4,T5,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T4,T5,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T5,T6
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	787807817	631162036	0	0
CheckNGreaterZero_A	2865	2865	0	0
GntImpliesReady_A	787807817	3842508	0	0
GntImpliesValid_A	787807817	3842508	0	0
GrantKnown_A	787807817	631162036	0	0
IdxKnown_A	787807817	631162036	0	0
IndexIsCorrect_A	787807817	3842508	0	0
LockArbDecision_A	787807817	0	0	0
NoReadyValidNoGrant_A	787807817	0	0	0
ReadyAndValidImplyGrant_A	787807817	3842508	0	0
ReqAndReadyImplyGrant_A	787807817	3842508	0	0
ReqImpliesValid_A	787807817	3842508	0	0
ReqStaysHighUntilGranted0_M	787807817	0	0	0
RoundRobin_A	787807817	5	0	955
ValidKnown_A	787807817	631162036	0	0
gen_data_port_assertion.DataFlow_A	787807817	3842508	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	787807817	631162036	0	0
T1	3155	2227	0	0
T2	1564	1505	0	0
T3	403730	401474	0	0
T4	473817	468521	0	0
T5	655792	413250	0	0
T6	10270	10196	0	0
T7	3432	2782	0	0
T8	1803122	984467	0	0
T9	10372	8497	0	0
T10	1148179	659288	0	0
T12	1664	832	0	0
T13	336192	168096	0	0
T14	197872	93752	0	0
T15	20383	20383	0	0
T16	0	73814	0	0
T17	0	27440	0	0
T18	0	19090	0	0
T19	0	214670	0	0
T23	1848	1848	0	0
T24	0	37664	0	0
T25	0	3360	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2865	2865	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	787807817	3842508	0	0
T4	473817	6609	0	0
T5	655792	6829	0	0
T6	10270	832	0	0
T7	3432	0	0	0
T8	1803122	10479	0	0
T9	10372	185	0	0
T10	1148179	18651	0	0
T11	2238	0	0	0
T12	7430	94	0	0
T13	513670	832	0	0
T14	197872	0	0	0
T15	40766	832	0	0
T20	0	4	0	0
T23	1848	143	0	0
T24	0	1869	0	0
T25	0	169	0	0
T26	0	237	0	0
T35	0	3003	0	0
T36	0	1079	0	0
T37	0	7223	0	0
T40	0	3370	0	0
T42	0	3820	0	0
T43	0	6051	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	787807817	3842508	0	0
T4	473817	6609	0	0
T5	655792	6829	0	0
T6	10270	832	0	0
T7	3432	0	0	0
T8	1803122	10479	0	0
T9	10372	185	0	0
T10	1148179	18651	0	0
T11	2238	0	0	0
T12	7430	94	0	0
T13	513670	832	0	0
T14	197872	0	0	0
T15	40766	832	0	0
T20	0	4	0	0
T23	1848	143	0	0
T24	0	1869	0	0
T25	0	169	0	0
T26	0	237	0	0
T35	0	3003	0	0
T36	0	1079	0	0
T37	0	7223	0	0
T40	0	3370	0	0
T42	0	3820	0	0
T43	0	6051	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	787807817	631162036	0	0
T1	3155	2227	0	0
T2	1564	1505	0	0
T3	403730	401474	0	0
T4	473817	468521	0	0
T5	655792	413250	0	0
T6	10270	10196	0	0
T7	3432	2782	0	0
T8	1803122	984467	0	0
T9	10372	8497	0	0
T10	1148179	659288	0	0
T12	1664	832	0	0
T13	336192	168096	0	0
T14	197872	93752	0	0
T15	20383	20383	0	0
T16	0	73814	0	0
T17	0	27440	0	0
T18	0	19090	0	0
T19	0	214670	0	0
T23	1848	1848	0	0
T24	0	37664	0	0
T25	0	3360	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	787807817	631162036	0	0
T1	3155	2227	0	0
T2	1564	1505	0	0
T3	403730	401474	0	0
T4	473817	468521	0	0
T5	655792	413250	0	0
T6	10270	10196	0	0
T7	3432	2782	0	0
T8	1803122	984467	0	0
T9	10372	8497	0	0
T10	1148179	659288	0	0
T12	1664	832	0	0
T13	336192	168096	0	0
T14	197872	93752	0	0
T15	20383	20383	0	0
T16	0	73814	0	0
T17	0	27440	0	0
T18	0	19090	0	0
T19	0	214670	0	0
T23	1848	1848	0	0
T24	0	37664	0	0
T25	0	3360	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	787807817	3842508	0	0
T4	473817	6609	0	0
T5	655792	6829	0	0
T6	10270	832	0	0
T7	3432	0	0	0
T8	1803122	10479	0	0
T9	10372	185	0	0
T10	1148179	18651	0	0
T11	2238	0	0	0
T12	7430	94	0	0
T13	513670	832	0	0
T14	197872	0	0	0
T15	40766	832	0	0
T20	0	4	0	0
T23	1848	143	0	0
T24	0	1869	0	0
T25	0	169	0	0
T26	0	237	0	0
T35	0	3003	0	0
T36	0	1079	0	0
T37	0	7223	0	0
T40	0	3370	0	0
T42	0	3820	0	0
T43	0	6051	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	787807817	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	787807817	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	787807817	3842508	0	0
T4	473817	6609	0	0
T5	655792	6829	0	0
T6	10270	832	0	0
T7	3432	0	0	0
T8	1803122	10479	0	0
T9	10372	185	0	0
T10	1148179	18651	0	0
T11	2238	0	0	0
T12	7430	94	0	0
T13	513670	832	0	0
T14	197872	0	0	0
T15	40766	832	0	0
T20	0	4	0	0
T23	1848	143	0	0
T24	0	1869	0	0
T25	0	169	0	0
T26	0	237	0	0
T35	0	3003	0	0
T36	0	1079	0	0
T37	0	7223	0	0
T40	0	3370	0	0
T42	0	3820	0	0
T43	0	6051	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	787807817	3842508	0	0
T4	473817	6609	0	0
T5	655792	6829	0	0
T6	10270	832	0	0
T7	3432	0	0	0
T8	1803122	10479	0	0
T9	10372	185	0	0
T10	1148179	18651	0	0
T11	2238	0	0	0
T12	7430	94	0	0
T13	513670	832	0	0
T14	197872	0	0	0
T15	40766	832	0	0
T20	0	4	0	0
T23	1848	143	0	0
T24	0	1869	0	0
T25	0	169	0	0
T26	0	237	0	0
T35	0	3003	0	0
T36	0	1079	0	0
T37	0	7223	0	0
T40	0	3370	0	0
T42	0	3820	0	0
T43	0	6051	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	787807817	3842508	0	0
T4	473817	6609	0	0
T5	655792	6829	0	0
T6	10270	832	0	0
T7	3432	0	0	0
T8	1803122	10479	0	0
T9	10372	185	0	0
T10	1148179	18651	0	0
T11	2238	0	0	0
T12	7430	94	0	0
T13	513670	832	0	0
T14	197872	0	0	0
T15	40766	832	0	0
T20	0	4	0	0
T23	1848	143	0	0
T24	0	1869	0	0
T25	0	169	0	0
T26	0	237	0	0
T35	0	3003	0	0
T36	0	1079	0	0
T37	0	7223	0	0
T40	0	3370	0	0
T42	0	3820	0	0
T43	0	6051	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	787807817	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	787807817	5	0	955
T27	305961	1	0	1
T33	0	1	0	0
T46	102272	0	0	1
T48	0	2	0	0
T49	0	1	0	0
T50	128479	0	0	1
T51	1049	0	0	1
T52	12998	0	0	1
T53	1461	0	0	1
T54	1083	0	0	1
T55	144439	0	0	1
T56	32069	0	0	1
T57	176443	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	787807817	631162036	0	0
T1	3155	2227	0	0
T2	1564	1505	0	0
T3	403730	401474	0	0
T4	473817	468521	0	0
T5	655792	413250	0	0
T6	10270	10196	0	0
T7	3432	2782	0	0
T8	1803122	984467	0	0
T9	10372	8497	0	0
T10	1148179	659288	0	0
T12	1664	832	0	0
T13	336192	168096	0	0
T14	197872	93752	0	0
T15	20383	20383	0	0
T16	0	73814	0	0
T17	0	27440	0	0
T18	0	19090	0	0
T19	0	214670	0	0
T23	1848	1848	0	0
T24	0	37664	0	0
T25	0	3360	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	787807817	3842508	0	0
T4	473817	6609	0	0
T5	655792	6829	0	0
T6	10270	832	0	0
T7	3432	0	0	0
T8	1803122	10479	0	0
T9	10372	185	0	0
T10	1148179	18651	0	0
T11	2238	0	0	0
T12	7430	94	0	0
T13	513670	832	0	0
T14	197872	0	0	0
T15	40766	832	0	0
T20	0	4	0	0
T23	1848	143	0	0
T24	0	1869	0	0
T25	0	169	0	0
T26	0	237	0	0
T35	0	3003	0	0
T36	0	1079	0	0
T37	0	7223	0	0
T40	0	3370	0	0
T42	0	3820	0	0
T43	0	6051	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T9,T10
1	0	Covered	T4,T9,T10

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T7
1	0	Unreachable
1	1	Covered	T4,T9,T10

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T9,T10
0	0	1	Unreachable
0	0	0	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T9,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	155128963	28114860	0	0
CheckNGreaterZero_A	955	955	0	0
GntImpliesReady_A	155128963	640162	0	0
GntImpliesValid_A	155128963	640162	0	0
GrantKnown_A	155128963	28114860	0	0
IdxKnown_A	155128963	28114860	0	0
IndexIsCorrect_A	155128963	640162	0	0
LockArbDecision_A	155128963	0	0	0
NoReadyValidNoGrant_A	155128963	0	0	0
ReadyAndValidImplyGrant_A	155128963	640162	0	0
ReqAndReadyImplyGrant_A	155128963	640162	0	0
ReqImpliesValid_A	155128963	640162	0	0
ReqStaysHighUntilGranted0_M	155128963	0	0	0
RoundRobin_A	155128963	0	0	0
ValidKnown_A	155128963	28114860	0	0
gen_data_port_assertion.DataFlow_A	155128963	640162	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155128963	28114860	0	0
T3	49023	46840	0	0
T4	341314	336072	0	0
T5	241304	0	0	0
T7	576	576	0	0
T8	817443	0	0	0
T9	1774	1728	0	0
T10	478622	143008	0	0
T12	832	832	0	0
T13	168096	0	0	0
T14	98936	93752	0	0
T23	0	1848	0	0
T24	0	37664	0	0
T25	0	3360	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	955	955	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155128963	640162	0	0
T4	341314	4394	0	0
T5	241304	0	0	0
T7	576	0	0	0
T8	817443	0	0	0
T9	1774	143	0	0
T10	478622	5811	0	0
T12	832	74	0	0
T13	168096	0	0	0
T14	98936	0	0	0
T15	20383	0	0	0
T23	0	97	0	0
T24	0	1869	0	0
T25	0	169	0	0
T35	0	3003	0	0
T37	0	2498	0	0
T40	0	1488	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155128963	640162	0	0
T4	341314	4394	0	0
T5	241304	0	0	0
T7	576	0	0	0
T8	817443	0	0	0
T9	1774	143	0	0
T10	478622	5811	0	0
T12	832	74	0	0
T13	168096	0	0	0
T14	98936	0	0	0
T15	20383	0	0	0
T23	0	97	0	0
T24	0	1869	0	0
T25	0	169	0	0
T35	0	3003	0	0
T37	0	2498	0	0
T40	0	1488	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155128963	28114860	0	0
T3	49023	46840	0	0
T4	341314	336072	0	0
T5	241304	0	0	0
T7	576	576	0	0
T8	817443	0	0	0
T9	1774	1728	0	0
T10	478622	143008	0	0
T12	832	832	0	0
T13	168096	0	0	0
T14	98936	93752	0	0
T23	0	1848	0	0
T24	0	37664	0	0
T25	0	3360	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155128963	28114860	0	0
T3	49023	46840	0	0
T4	341314	336072	0	0
T5	241304	0	0	0
T7	576	576	0	0
T8	817443	0	0	0
T9	1774	1728	0	0
T10	478622	143008	0	0
T12	832	832	0	0
T13	168096	0	0	0
T14	98936	93752	0	0
T23	0	1848	0	0
T24	0	37664	0	0
T25	0	3360	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155128963	640162	0	0
T4	341314	4394	0	0
T5	241304	0	0	0
T7	576	0	0	0
T8	817443	0	0	0
T9	1774	143	0	0
T10	478622	5811	0	0
T12	832	74	0	0
T13	168096	0	0	0
T14	98936	0	0	0
T15	20383	0	0	0
T23	0	97	0	0
T24	0	1869	0	0
T25	0	169	0	0
T35	0	3003	0	0
T37	0	2498	0	0
T40	0	1488	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155128963	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155128963	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155128963	640162	0	0
T4	341314	4394	0	0
T5	241304	0	0	0
T7	576	0	0	0
T8	817443	0	0	0
T9	1774	143	0	0
T10	478622	5811	0	0
T12	832	74	0	0
T13	168096	0	0	0
T14	98936	0	0	0
T15	20383	0	0	0
T23	0	97	0	0
T24	0	1869	0	0
T25	0	169	0	0
T35	0	3003	0	0
T37	0	2498	0	0
T40	0	1488	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155128963	640162	0	0
T4	341314	4394	0	0
T5	241304	0	0	0
T7	576	0	0	0
T8	817443	0	0	0
T9	1774	143	0	0
T10	478622	5811	0	0
T12	832	74	0	0
T13	168096	0	0	0
T14	98936	0	0	0
T15	20383	0	0	0
T23	0	97	0	0
T24	0	1869	0	0
T25	0	169	0	0
T35	0	3003	0	0
T37	0	2498	0	0
T40	0	1488	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155128963	640162	0	0
T4	341314	4394	0	0
T5	241304	0	0	0
T7	576	0	0	0
T8	817443	0	0	0
T9	1774	143	0	0
T10	478622	5811	0	0
T12	832	74	0	0
T13	168096	0	0	0
T14	98936	0	0	0
T15	20383	0	0	0
T23	0	97	0	0
T24	0	1869	0	0
T25	0	169	0	0
T35	0	3003	0	0
T37	0	2498	0	0
T40	0	1488	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	155128963	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155128963	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155128963	28114860	0	0
T3	49023	46840	0	0
T4	341314	336072	0	0
T5	241304	0	0	0
T7	576	576	0	0
T8	817443	0	0	0
T9	1774	1728	0	0
T10	478622	143008	0	0
T12	832	832	0	0
T13	168096	0	0	0
T14	98936	93752	0	0
T23	0	1848	0	0
T24	0	37664	0	0
T25	0	3360	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155128963	640162	0	0
T4	341314	4394	0	0
T5	241304	0	0	0
T7	576	0	0	0
T8	817443	0	0	0
T9	1774	143	0	0
T10	478622	5811	0	0
T12	832	74	0	0
T13	168096	0	0	0
T14	98936	0	0	0
T15	20383	0	0	0
T23	0	97	0	0
T24	0	1869	0	0
T25	0	169	0	0
T35	0	3003	0	0
T37	0	2498	0	0
T40	0	1488	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T8,T10

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T10
1	0	Covered	T5,T8,T10

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T10
1	0	Unreachable
1	1	Covered	T5,T8,T10

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T8,T10
0	0	1	Unreachable
0	0	0	Covered	T5,T8,T10

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	155128963	125583088	0	0
CheckNGreaterZero_A	955	955	0	0
GntImpliesReady_A	155128963	816360	0	0
GntImpliesValid_A	155128963	816360	0	0
GrantKnown_A	155128963	125583088	0	0
IdxKnown_A	155128963	125583088	0	0
IndexIsCorrect_A	155128963	816360	0	0
LockArbDecision_A	155128963	0	0	0
NoReadyValidNoGrant_A	155128963	0	0	0
ReadyAndValidImplyGrant_A	155128963	816360	0	0
ReqAndReadyImplyGrant_A	155128963	816360	0	0
ReqImpliesValid_A	155128963	816360	0	0
ReqStaysHighUntilGranted0_M	155128963	0	0	0
RoundRobin_A	155128963	0	0	0
ValidKnown_A	155128963	125583088	0	0
gen_data_port_assertion.DataFlow_A	155128963	816360	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155128963	125583088	0	0
T5	241304	240156	0	0
T7	576	0	0	0
T8	817443	816236	0	0
T9	1774	0	0	0
T10	478622	325355	0	0
T12	832	0	0	0
T13	168096	168096	0	0
T14	98936	0	0	0
T15	20383	20383	0	0
T16	0	73814	0	0
T17	0	27440	0	0
T18	0	19090	0	0
T19	0	214670	0	0
T20	0	162400	0	0
T23	1848	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	955	955	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155128963	816360	0	0
T5	241304	3300	0	0
T7	576	0	0	0
T8	817443	2080	0	0
T9	1774	0	0	0
T10	478622	3257	0	0
T12	832	0	0	0
T13	168096	0	0	0
T14	98936	0	0	0
T15	20383	0	0	0
T20	0	4	0	0
T23	1848	0	0	0
T26	0	237	0	0
T36	0	1079	0	0
T37	0	4725	0	0
T40	0	1882	0	0
T42	0	3820	0	0
T43	0	6051	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155128963	816360	0	0
T5	241304	3300	0	0
T7	576	0	0	0
T8	817443	2080	0	0
T9	1774	0	0	0
T10	478622	3257	0	0
T12	832	0	0	0
T13	168096	0	0	0
T14	98936	0	0	0
T15	20383	0	0	0
T20	0	4	0	0
T23	1848	0	0	0
T26	0	237	0	0
T36	0	1079	0	0
T37	0	4725	0	0
T40	0	1882	0	0
T42	0	3820	0	0
T43	0	6051	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155128963	125583088	0	0
T5	241304	240156	0	0
T7	576	0	0	0
T8	817443	816236	0	0
T9	1774	0	0	0
T10	478622	325355	0	0
T12	832	0	0	0
T13	168096	168096	0	0
T14	98936	0	0	0
T15	20383	20383	0	0
T16	0	73814	0	0
T17	0	27440	0	0
T18	0	19090	0	0
T19	0	214670	0	0
T20	0	162400	0	0
T23	1848	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155128963	125583088	0	0
T5	241304	240156	0	0
T7	576	0	0	0
T8	817443	816236	0	0
T9	1774	0	0	0
T10	478622	325355	0	0
T12	832	0	0	0
T13	168096	168096	0	0
T14	98936	0	0	0
T15	20383	20383	0	0
T16	0	73814	0	0
T17	0	27440	0	0
T18	0	19090	0	0
T19	0	214670	0	0
T20	0	162400	0	0
T23	1848	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155128963	816360	0	0
T5	241304	3300	0	0
T7	576	0	0	0
T8	817443	2080	0	0
T9	1774	0	0	0
T10	478622	3257	0	0
T12	832	0	0	0
T13	168096	0	0	0
T14	98936	0	0	0
T15	20383	0	0	0
T20	0	4	0	0
T23	1848	0	0	0
T26	0	237	0	0
T36	0	1079	0	0
T37	0	4725	0	0
T40	0	1882	0	0
T42	0	3820	0	0
T43	0	6051	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155128963	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155128963	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155128963	816360	0	0
T5	241304	3300	0	0
T7	576	0	0	0
T8	817443	2080	0	0
T9	1774	0	0	0
T10	478622	3257	0	0
T12	832	0	0	0
T13	168096	0	0	0
T14	98936	0	0	0
T15	20383	0	0	0
T20	0	4	0	0
T23	1848	0	0	0
T26	0	237	0	0
T36	0	1079	0	0
T37	0	4725	0	0
T40	0	1882	0	0
T42	0	3820	0	0
T43	0	6051	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155128963	816360	0	0
T5	241304	3300	0	0
T7	576	0	0	0
T8	817443	2080	0	0
T9	1774	0	0	0
T10	478622	3257	0	0
T12	832	0	0	0
T13	168096	0	0	0
T14	98936	0	0	0
T15	20383	0	0	0
T20	0	4	0	0
T23	1848	0	0	0
T26	0	237	0	0
T36	0	1079	0	0
T37	0	4725	0	0
T40	0	1882	0	0
T42	0	3820	0	0
T43	0	6051	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155128963	816360	0	0
T5	241304	3300	0	0
T7	576	0	0	0
T8	817443	2080	0	0
T9	1774	0	0	0
T10	478622	3257	0	0
T12	832	0	0	0
T13	168096	0	0	0
T14	98936	0	0	0
T15	20383	0	0	0
T20	0	4	0	0
T23	1848	0	0	0
T26	0	237	0	0
T36	0	1079	0	0
T37	0	4725	0	0
T40	0	1882	0	0
T42	0	3820	0	0
T43	0	6051	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	155128963	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155128963	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155128963	125583088	0	0
T5	241304	240156	0	0
T7	576	0	0	0
T8	817443	816236	0	0
T9	1774	0	0	0
T10	478622	325355	0	0
T12	832	0	0	0
T13	168096	168096	0	0
T14	98936	0	0	0
T15	20383	20383	0	0
T16	0	73814	0	0
T17	0	27440	0	0
T18	0	19090	0	0
T19	0	214670	0	0
T20	0	162400	0	0
T23	1848	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155128963	816360	0	0
T5	241304	3300	0	0
T7	576	0	0	0
T8	817443	2080	0	0
T9	1774	0	0	0
T10	478622	3257	0	0
T12	832	0	0	0
T13	168096	0	0	0
T14	98936	0	0	0
T15	20383	0	0	0
T20	0	4	0	0
T23	1848	0	0	0
T26	0	237	0	0
T36	0	1079	0	0
T37	0	4725	0	0
T40	0	1882	0	0
T42	0	3820	0	0
T43	0	6051	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T8
1	0	Covered	T4,T5,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T4,T5,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T5,T6
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	477549891	477464088	0	0
CheckNGreaterZero_A	955	955	0	0
GntImpliesReady_A	477549891	2385986	0	0
GntImpliesValid_A	477549891	2385986	0	0
GrantKnown_A	477549891	477464088	0	0
IdxKnown_A	477549891	477464088	0	0
IndexIsCorrect_A	477549891	2385986	0	0
LockArbDecision_A	477549891	0	0	0
NoReadyValidNoGrant_A	477549891	0	0	0
ReadyAndValidImplyGrant_A	477549891	2385986	0	0
ReqAndReadyImplyGrant_A	477549891	2385986	0	0
ReqImpliesValid_A	477549891	2385986	0	0
ReqStaysHighUntilGranted0_M	477549891	0	0	0
RoundRobin_A	477549891	5	0	955
ValidKnown_A	477549891	477464088	0	0
gen_data_port_assertion.DataFlow_A	477549891	2385986	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477549891	477464088	0	0
T1	3155	2227	0	0
T2	1564	1505	0	0
T3	354707	354634	0	0
T4	132503	132449	0	0
T5	173184	173094	0	0
T6	10270	10196	0	0
T7	2280	2206	0	0
T8	168236	168231	0	0
T9	6824	6769	0	0
T10	190935	190925	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	955	955	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477549891	2385986	0	0
T4	132503	2215	0	0
T5	173184	3529	0	0
T6	10270	832	0	0
T7	2280	0	0	0
T8	168236	8399	0	0
T9	6824	42	0	0
T10	190935	9583	0	0
T11	2238	0	0	0
T12	5766	20	0	0
T13	177478	832	0	0
T15	0	832	0	0
T23	0	46	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477549891	2385986	0	0
T4	132503	2215	0	0
T5	173184	3529	0	0
T6	10270	832	0	0
T7	2280	0	0	0
T8	168236	8399	0	0
T9	6824	42	0	0
T10	190935	9583	0	0
T11	2238	0	0	0
T12	5766	20	0	0
T13	177478	832	0	0
T15	0	832	0	0
T23	0	46	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477549891	477464088	0	0
T1	3155	2227	0	0
T2	1564	1505	0	0
T3	354707	354634	0	0
T4	132503	132449	0	0
T5	173184	173094	0	0
T6	10270	10196	0	0
T7	2280	2206	0	0
T8	168236	168231	0	0
T9	6824	6769	0	0
T10	190935	190925	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477549891	477464088	0	0
T1	3155	2227	0	0
T2	1564	1505	0	0
T3	354707	354634	0	0
T4	132503	132449	0	0
T5	173184	173094	0	0
T6	10270	10196	0	0
T7	2280	2206	0	0
T8	168236	168231	0	0
T9	6824	6769	0	0
T10	190935	190925	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477549891	2385986	0	0
T4	132503	2215	0	0
T5	173184	3529	0	0
T6	10270	832	0	0
T7	2280	0	0	0
T8	168236	8399	0	0
T9	6824	42	0	0
T10	190935	9583	0	0
T11	2238	0	0	0
T12	5766	20	0	0
T13	177478	832	0	0
T15	0	832	0	0
T23	0	46	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477549891	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477549891	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477549891	2385986	0	0
T4	132503	2215	0	0
T5	173184	3529	0	0
T6	10270	832	0	0
T7	2280	0	0	0
T8	168236	8399	0	0
T9	6824	42	0	0
T10	190935	9583	0	0
T11	2238	0	0	0
T12	5766	20	0	0
T13	177478	832	0	0
T15	0	832	0	0
T23	0	46	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477549891	2385986	0	0
T4	132503	2215	0	0
T5	173184	3529	0	0
T6	10270	832	0	0
T7	2280	0	0	0
T8	168236	8399	0	0
T9	6824	42	0	0
T10	190935	9583	0	0
T11	2238	0	0	0
T12	5766	20	0	0
T13	177478	832	0	0
T15	0	832	0	0
T23	0	46	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477549891	2385986	0	0
T4	132503	2215	0	0
T5	173184	3529	0	0
T6	10270	832	0	0
T7	2280	0	0	0
T8	168236	8399	0	0
T9	6824	42	0	0
T10	190935	9583	0	0
T11	2238	0	0	0
T12	5766	20	0	0
T13	177478	832	0	0
T15	0	832	0	0
T23	0	46	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	477549891	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477549891	5	0	955
T27	305961	1	0	1
T33	0	1	0	0
T46	102272	0	0	1
T48	0	2	0	0
T49	0	1	0	0
T50	128479	0	0	1
T51	1049	0	0	1
T52	12998	0	0	1
T53	1461	0	0	1
T54	1083	0	0	1
T55	144439	0	0	1
T56	32069	0	0	1
T57	176443	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477549891	477464088	0	0
T1	3155	2227	0	0
T2	1564	1505	0	0
T3	354707	354634	0	0
T4	132503	132449	0	0
T5	173184	173094	0	0
T6	10270	10196	0	0
T7	2280	2206	0	0
T8	168236	168231	0	0
T9	6824	6769	0	0
T10	190935	190925	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477549891	2385986	0	0
T4	132503	2215	0	0
T5	173184	3529	0	0
T6	10270	832	0	0
T7	2280	0	0	0
T8	168236	8399	0	0
T9	6824	42	0	0
T10	190935	9583	0	0
T11	2238	0	0	0
T12	5766	20	0	0
T13	177478	832	0	0
T15	0	832	0	0
T23	0	46	0	0