Unified Coverage Report :: Module :: spi_readcmd

Module : spi_readcmd

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	96.32	100.00		80.00	84.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_readcmd.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_readcmd	92.19	96.32	100.00		80.00	84.62	100.00

---

Module Instance : tb.dut.u_readcmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	96.32	100.00		80.00	84.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.30	93.62	90.32		87.50	84.15	90.91

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_addr_latch_pulse	100.00	100.00	100.00			100.00
u_readbuffer	68.17	83.51	82.93			72.92	33.33
u_readsram	95.10	97.79	86.54		100.00	91.18	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spi_readcmd

	Line No.	Total	Covered	Percent
TOTAL		136	131	96.32
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	190	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	341	1	1	100.00
ALWAYS	354	4	4	100.00
ALWAYS	370	4	4	100.00
CONT_ASSIGN	379	1	1	100.00
ALWAYS	382	12	12	100.00
CONT_ASSIGN	405	1	1	100.00
CONT_ASSIGN	406	1	1	100.00
CONT_ASSIGN	409	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
ALWAYS	428	3	3	100.00
ALWAYS	436	7	7	100.00
ALWAYS	457	6	6	100.00
CONT_ASSIGN	466	1	1	100.00
ALWAYS	470	12	12	100.00
CONT_ASSIGN	497	1	1	100.00
CONT_ASSIGN	498	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	502	1	1	100.00
ALWAYS	514	8	8	100.00
CONT_ASSIGN	530	1	1	100.00
ALWAYS	535	5	5	100.00
ALWAYS	553	4	4	100.00
CONT_ASSIGN	566	1	1	100.00
ALWAYS	576	3	3	100.00
ALWAYS	584	48	43	89.58
CONT_ASSIGN	721	1	1	100.00
CONT_ASSIGN	722	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_readcmd.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_readcmd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
184	1	1
187	1	1
190	1	1
193	1	1
334	1	1
341	1	1
354	1	1
355	1	1
356	1	1
357	1	1
			MISSING_ELSE
370	1	1
371	1	1
372	1	1
375	1	1
			MISSING_ELSE
379	1	1
382	1	1
383	1	1
385	1	1
387	1	1
388	1	1
391	1	1
392	1	1
394	1	1
395	1	1
396	1	1
398	1	1
399	1	1
			MISSING_ELSE
405	1	1
406	1	1
409	1	1
425	1	1
428	1	1
429	1	1
431	1	1
436	1	1
437	1	1
444	1	1
446	1	1
447	1	1
448	1	1
450	1	1
			==> MISSING_ELSE
457	1	1
458	1	1
459	1	1
461	1	1
462	1	1
463	1	1
			MISSING_ELSE
466	1	1
470	1	1
471	1	1
472	1	1
473	1	1
474	1	1
475	1	1
476	1	1
479	1	1
480	1	1
481	1	1
482	1	1
483	1	1
			MISSING_ELSE
497	1	1
498	1	1
501	1	1
502	1	1
514	2	2
515	1	1
517	1	1
518	1	1
521	1	1
522	1	1
524	1	1
			MISSING_ELSE
530	1	1
535	1	1
536	1	1
537	1	1
539	1	1
540	1	1
553	1	1
554	1	1
555	1	1
561	1	1
			MISSING_ELSE
566	1	1
576	1	1
577	1	1
579	1	1
584	1	1
586	1	1
589	1	1
590	1	1
591	1	1
592	1	1
594	1	1
595	1	1
597	1	1
598	1	1
600	1	1
602	1	1
603	1	1
605	1	1
607	1	1
610	1	1
612	1	1
			MISSING_ELSE
617	1	1
619	1	1
620	1	1
			MISSING_ELSE
623	1	1
626	1	1
632	1	1
635	1	1
636	1	1
637	1	1
642	1	1
644	1	1
649	0	1
			MISSING_ELSE
660	0	1
661	0	1
663	0	1
			==> MISSING_ELSE
668	1	1
669	1	1
670	1	1
671	1	1
			MISSING_ELSE
676	1	1
680	1	1
685	1	1
686	1	1
687	1	1
688	1	1
692	1	1
694	1	1
697	1	1
700	1	1
701	1	1
			MISSING_ELSE
706	0	1
721	1	1
722	1	1

---

Cond Coverage for Module : spi_readcmd

	Total	Covered	Percent
Conditions	66	66	100.00
Logical	66	66	100.00
Non-Logical	0	0
Event	0	0

 LINE       334
 EXPRESSION (sel_dp_i == DpReadSFDP)
            ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T8,T10

 LINE       341
 EXPRESSION (spi_mode_i == FlashMode)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       372
 EXPRESSION ((main_st == MainOutput) && (sel_dp_i == DpReadCmd) && addr_latch_en && ( ! (mailbox_en_i && addr_q_in_mailbox) ) && spid_in_flashmode)
             -----------1-----------    -----------2-----------    ------3------    --------------------4--------------------    --------5--------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	1	1	1	1	Covered	T10,T15,T18
1	0	1	1	1	Covered	T10,T35,T40
1	1	0	1	1	Covered	T15,T18,T39
1	1	1	0	1	Covered	T10,T35,T40
1	1	1	1	0	Covered	T5,T8,T16
1	1	1	1	1	Covered	T15,T18,T39

 LINE       372
 SUB-EXPRESSION (main_st == MainOutput)
                -----------1-----------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T5,T8,T10

 LINE       372
 SUB-EXPRESSION (sel_dp_i == DpReadCmd)
                -----------1-----------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T5,T8,T10

 LINE       372
 SUB-EXPRESSION ( ! (mailbox_en_i && addr_q_in_mailbox) )
                    -----------------1-----------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T5,T8,T10

 LINE       372
 SUB-EXPRESSION (mailbox_en_i && addr_q_in_mailbox)
                 ------1-----    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T5,T8,T10
1	1	Covered	T5,T8,T10

 LINE       392
 EXPRESSION (addr_shift_en && s2p_valid_i)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T10
1	0	Covered	T5,T8,T10
1	1	Covered	T5,T8,T10

 LINE       405
 EXPRESSION (addr_cnt_d == 5'd2)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T8,T10

 LINE       406
 EXPRESSION (addr_cnt_d == 5'b1)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T8,T10

 LINE       409
 EXPRESSION (addr_cnt_d == 5'b0)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       444
 EXPRESSION ((cmdinfo_addr_mode == Addr4B) ? 5'd31 : 5'd23)
             --------------1--------------

-1-	Status	Tests
0	Covered	T5,T8,T10
1	Covered	T5,T8,T10

 LINE       444
 SUB-EXPRESSION (cmdinfo_addr_mode == Addr4B)
                --------------1--------------

-1-	Status	Tests
0	Covered	T5,T8,T10
1	Covered	T5,T8,T10

 LINE       446
 EXPRESSION (addr_cnt_q == '0)
            ---------1--------

-1-	Status	Tests
0	Covered	T5,T8,T10
1	Covered	T1,T2,T3

 LINE       501
 EXPRESSION (mailbox_masked_addr_d == mailbox_addr_i)
            --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       502
 EXPRESSION (mailbox_masked_addr_q == mailbox_addr_i)
            --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       515
 EXPRESSION (sram_req && mailbox_en_i && cfg_intercept_en_mbx_i && addr_d_in_mailbox)
             ----1---    ------2-----    -----------3----------    --------4--------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T8,T10,T19
1	0	1	1	Covered	T5,T8,T37
1	1	0	1	Covered	T5,T8,T10
1	1	1	0	Covered	T8,T10,T18
1	1	1	1	Covered	T8,T10,T19

 LINE       518
 EXPRESSION (mailbox_en_i && cfg_intercept_en_mbx_i && addr_d_in_mailbox && (bitcnt == 3'b0))
             ------1-----    -----------2----------    --------3--------    --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T5,T8,T37
1	0	1	1	Covered	T5,T8,T10
1	1	0	1	Covered	T8,T10,T13
1	1	1	0	Covered	T8,T10,T19
1	1	1	1	Covered	T8,T10,T19

 LINE       518
 SUB-EXPRESSION (bitcnt == 3'b0)
                --------1-------

-1-	Status	Tests
0	Covered	T5,T8,T10
1	Covered	T5,T8,T10

 LINE       522
 EXPRESSION (((!addr_d_in_mailbox)) && (bitcnt == 3'b0))
             -----------1----------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T10
1	0	Covered	T5,T8,T10
1	1	Covered	T5,T8,T10

 LINE       522
 SUB-EXPRESSION (bitcnt == 3'b0)
                --------1-------

-1-	Status	Tests
0	Covered	T5,T8,T10
1	Covered	T5,T8,T10

 LINE       566
 EXPRESSION ((main_st == MainOutput) && (addr_q[9:0] == '1))
             -----------1-----------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T15,T18,T37
1	0	Covered	T5,T8,T10
1	1	Covered	T5,T8,T10

 LINE       566
 SUB-EXPRESSION (main_st == MainOutput)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T8,T10

 LINE       566
 SUB-EXPRESSION (addr_q[9:0] == '1)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T8,T10

 LINE       692
 EXPRESSION (bitcnt == 3'b0)
            --------1-------

-1-	Status	Tests
0	Covered	T5,T8,T10
1	Covered	T5,T8,T10

 LINE       735
 EXPRESSION (sel_dp_i == DpReadSFDP)
            ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T8,T10

---

FSM Coverage for Module : spi_readcmd

Summary for FSM :: main_st

	Total	Covered	Percent
States	5	4	80.00	(Not included in score)
Transitions	5	4	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: main_st

---

states	Line No.	Covered	Tests
MainAddress	610	Covered	T5,T8,T10
MainDummy	642	Covered	T5,T8,T10
MainError	653	Not Covered
MainMByte	649	Excluded
MainOutput	635	Covered	T5,T8,T10
MainReset	606	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
MainAddress->MainDummy	642	Covered	T5,T8,T10
MainAddress->MainError	653	Not Covered
MainAddress->MainMByte	649	Excluded
MainAddress->MainOutput	635	Covered	T5,T8,T10
MainDummy->MainOutput	669	Covered	T5,T8,T10
MainMByte->MainDummy	661	Excluded
MainReset->MainAddress	610	Covered	T5,T8,T10

---

Branch Coverage for Module : spi_readcmd

	Line No.	Total	Covered	Percent
Branches		65	55	84.62
IF	354	3	3	100.00
IF	370	3	3	100.00
IF	385	5	5	100.00
IF	428	2	2	100.00
IF	437	5	4	80.00
IF	457	4	4	100.00
IF	470	10	8	80.00
IF	514	5	5	100.00
IF	535	2	2	100.00
IF	553	3	3	100.00
IF	576	2	2	100.00
CASE	605	21	14	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_readcmd.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_readcmd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	354	if ((!rst_ni))
-2-:	356	if (addr_latch_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T5,T8,T10
0	0	Covered	T5,T8,T10

	LineNo.	Expression
-1-:	370	if ((!sys_rst_ni))
-2-:	372	if ((((((main_st == MainOutput) && (sel_dp_i == DpReadCmd)) && addr_latch_en) && (!(mailbox_en_i && addr_q_in_mailbox))) && spid_in_flashmode))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T15,T18,T39
0	0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	385	if (addr_ready_in_word)
-2-:	388	if (addr_ready_in_halfword)
-3-:	392	if ((addr_shift_en && s2p_valid_i))
-4-:	396	if (addr_inc)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T5,T8,T10
0	1	-	-	Covered	T5,T8,T10
0	0	1	-	Covered	T5,T8,T10
0	0	0	1	Covered	T5,T8,T10
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	428	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T8,T10

	LineNo.	Expression
-1-:	437	if (addr_cnt_set)
-2-:	444	((cmdinfo_addr_mode == Addr4B)) ? 
-3-:	446	if ((addr_cnt_q == '0))
-4-:	448	if (addr_shift_en)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T5,T8,T10
1	0	-	-	Covered	T5,T8,T10
0	-	1	-	Covered	T1,T2,T3
0	-	0	1	Covered	T5,T8,T10
0	-	0	0	Not Covered

	LineNo.	Expression
-1-:	457	if ((!rst_ni))
-2-:	459	if (load_dummycnt)
-3-:	462	if ((!dummycnt_eq_zero))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T8,T10
0	0	1	Covered	T5,T8,T10
0	0	0	Covered	T5,T8,T10

	LineNo.	Expression
-1-:	470	if ((!rst_ni))
-2-:	472	if (bitcnt_update)
-3-:	473	case (cmd_info_i.payload_en)
-4-:	479	if (bitcnt_dec)
-5-:	480	case (cmd_info_i.payload_en)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	4'b0010	-	-	Covered	T5,T8,T10
0	1	4'b0011	-	-	Covered	T5,T8,T10
0	1	4'b1111	-	-	Covered	T5,T8,T10
0	1	default	-	-	Not Covered
0	0	-	1	4'b0010	Covered	T5,T8,T10
0	0	-	1	4'b0011	Covered	T5,T8,T10
0	0	-	1	4'b1111	Covered	T5,T8,T10
0	0	-	1	default	Not Covered
0	0	-	0	-	Covered	T5,T8,T10

	LineNo.	Expression
-1-:	514	if ((!rst_ni))
-2-:	515	if ((((sram_req && mailbox_en_i) && cfg_intercept_en_mbx_i) && addr_d_in_mailbox))
-3-:	518	if ((((mailbox_en_i && cfg_intercept_en_mbx_i) && addr_d_in_mailbox) && (bitcnt == 3'b0)))
-4-:	522	if (((!addr_d_in_mailbox) && (bitcnt == 3'b0)))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T8,T10,T19
0	0	1	-	Covered	T8,T10,T19
0	0	0	1	Covered	T5,T8,T10
0	0	0	0	Covered	T5,T8,T10

	LineNo.	Expression
-1-:	535	if ((!rst_out_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T8,T10

	LineNo.	Expression
-1-:	553	if ((!sys_rst_ni))
-2-:	555	if (readbuf_flip)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T5,T8,T10
0	0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	576	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T8,T10

	LineNo.	Expression
-1-:	605	case (main_st)
-2-:	607	if ((sel_dp_i inside {DpReadCmd, DpReadSFDP}))
-3-:	619	if (addr_ready_in_word)
-4-:	623	if (addr_latched)
-5-:	632	case ({cmd_info_i.mbyte_en, cmd_info_i.dummy_en})
-6-:	660	if (s2p_valid_i)
-7-:	668	if (dummycnt_eq_zero)
-8-:	685	case (cmd_info_i.payload_en)
-9-:	692	if ((bitcnt == 3'b0))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
MainReset	1	-	-	-	-	-	-	-	Covered	T5,T8,T10
MainReset	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
MainAddress	-	1	-	-	-	-	-	-	Covered	T5,T8,T10
MainAddress	-	0	-	-	-	-	-	-	Covered	T5,T8,T10
MainAddress	-	-	1	2'b00	-	-	-	-	Covered	T5,T8,T10
MainAddress	-	-	1	2'b01	-	-	-	-	Covered	T5,T8,T10
MainAddress	-	-	1	2'b1z	-	-	-	-	Not Covered
MainAddress	-	-	1	default	-	-	-	-	Not Covered
MainAddress	-	-	0	-	-	-	-	-	Covered	T5,T8,T10
MainMByte	-	-	-	-	1	-	-	-	Not Covered
MainMByte	-	-	-	-	0	-	-	-	Not Covered
MainDummy	-	-	-	-	-	1	-	-	Covered	T5,T8,T10
MainDummy	-	-	-	-	-	0	-	-	Covered	T5,T8,T10
MainOutput	-	-	-	-	-	-	4'b0010	-	Covered	T5,T8,T10
MainOutput	-	-	-	-	-	-	4'b0011	-	Covered	T5,T8,T10
MainOutput	-	-	-	-	-	-	4'b1111	-	Covered	T5,T8,T10
MainOutput	-	-	-	-	-	-	default	-	Not Covered
MainOutput	-	-	-	-	-	-	-	1	Covered	T5,T8,T10
MainOutput	-	-	-	-	-	-	-	0	Covered	T5,T8,T10
MainError	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	Not Covered

---

Assert Coverage for Module : spi_readcmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AddrIncNotAssertInAddressState_A	155128963	4801317	0	0
MailboxSizeMatch_M	155128963	125583088	0	0
ValidCmdConfig_A	155128963	213792	0	0

AddrIncNotAssertInAddressState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155128963	4801317	0	0
T5	241304	11793	0	0
T7	576	0	0	0
T8	817443	36025	0	0
T9	1774	0	0	0
T10	478622	6782	0	0
T12	832	0	0	0
T13	168096	0	0	0
T14	98936	0	0	0
T15	20383	3886	0	0
T16	0	3468	0	0
T18	0	3238	0	0
T19	0	4040	0	0
T20	0	3862	0	0
T23	1848	0	0	0
T37	0	65754	0	0
T41	0	16068	0	0

MailboxSizeMatch_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	155128963	125583088	0	0
T5	241304	240156	0	0
T7	576	0	0	0
T8	817443	816236	0	0
T9	1774	0	0	0
T10	478622	325355	0	0
T12	832	0	0	0
T13	168096	168096	0	0
T14	98936	0	0	0
T15	20383	20383	0	0
T16	0	73814	0	0
T17	0	27440	0	0
T18	0	19090	0	0
T19	0	214670	0	0
T20	0	162400	0	0
T23	1848	0	0	0

ValidCmdConfig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155128963	213792	0	0
T5	241304	516	0	0
T7	576	0	0	0
T8	817443	1064	0	0
T9	1774	0	0	0
T10	478622	378	0	0
T12	832	0	0	0
T13	168096	0	0	0
T14	98936	0	0	0
T15	20383	184	0	0
T16	0	46	0	0
T18	0	216	0	0
T19	0	124	0	0
T20	0	124	0	0
T23	1848	0	0	0
T37	0	2094	0	0
T41	0	416	0	0