Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
3621 |
0 |
0 |
T62 |
19028 |
5 |
0 |
0 |
T64 |
102558 |
5 |
0 |
0 |
T81 |
20498 |
367 |
0 |
0 |
T82 |
11940 |
130 |
0 |
0 |
T84 |
19410 |
294 |
0 |
0 |
T85 |
13373 |
166 |
0 |
0 |
T87 |
6566 |
117 |
0 |
0 |
T89 |
13451 |
213 |
0 |
0 |
T92 |
3677 |
7 |
0 |
0 |
T93 |
10139 |
5 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
2259 |
0 |
0 |
T63 |
5036 |
8 |
0 |
0 |
T64 |
102558 |
91 |
0 |
0 |
T93 |
10139 |
18 |
0 |
0 |
T98 |
11888 |
12 |
0 |
0 |
T100 |
90683 |
195 |
0 |
0 |
T105 |
4148 |
1 |
0 |
0 |
T115 |
3960 |
5 |
0 |
0 |
T127 |
14364 |
15 |
0 |
0 |
T128 |
7991 |
8 |
0 |
0 |
T129 |
14619 |
13 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
2403 |
0 |
0 |
T63 |
5036 |
8 |
0 |
0 |
T64 |
102558 |
100 |
0 |
0 |
T93 |
10139 |
20 |
0 |
0 |
T98 |
11888 |
6 |
0 |
0 |
T100 |
90683 |
255 |
0 |
0 |
T107 |
180348 |
417 |
0 |
0 |
T127 |
14364 |
13 |
0 |
0 |
T128 |
7991 |
13 |
0 |
0 |
T129 |
14619 |
15 |
0 |
0 |
T130 |
19558 |
37 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
2800 |
0 |
0 |
T63 |
5036 |
20 |
0 |
0 |
T64 |
102558 |
218 |
0 |
0 |
T93 |
10139 |
13 |
0 |
0 |
T98 |
11888 |
10 |
0 |
0 |
T100 |
90683 |
168 |
0 |
0 |
T105 |
4148 |
12 |
0 |
0 |
T115 |
3960 |
2 |
0 |
0 |
T127 |
14364 |
12 |
0 |
0 |
T128 |
7991 |
10 |
0 |
0 |
T129 |
14619 |
10 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
9970 |
0 |
0 |
T63 |
5036 |
6 |
0 |
0 |
T64 |
102558 |
1691 |
0 |
0 |
T93 |
10139 |
240 |
0 |
0 |
T98 |
11888 |
121 |
0 |
0 |
T100 |
90683 |
248 |
0 |
0 |
T105 |
4148 |
1 |
0 |
0 |
T115 |
3960 |
61 |
0 |
0 |
T127 |
14364 |
43 |
0 |
0 |
T128 |
7991 |
278 |
0 |
0 |
T129 |
14619 |
197 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
9613 |
0 |
0 |
T63 |
5036 |
8 |
0 |
0 |
T64 |
102558 |
1390 |
0 |
0 |
T93 |
10139 |
14 |
0 |
0 |
T98 |
11888 |
227 |
0 |
0 |
T100 |
90683 |
220 |
0 |
0 |
T105 |
4148 |
9 |
0 |
0 |
T115 |
3960 |
3 |
0 |
0 |
T127 |
14364 |
139 |
0 |
0 |
T128 |
7991 |
132 |
0 |
0 |
T129 |
14619 |
168 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
9186 |
0 |
0 |
T63 |
5036 |
7 |
0 |
0 |
T64 |
102558 |
1079 |
0 |
0 |
T93 |
10139 |
3 |
0 |
0 |
T98 |
11888 |
253 |
0 |
0 |
T100 |
90683 |
224 |
0 |
0 |
T105 |
4148 |
6 |
0 |
0 |
T127 |
14364 |
135 |
0 |
0 |
T128 |
7991 |
118 |
0 |
0 |
T129 |
14619 |
129 |
0 |
0 |
T130 |
19558 |
84 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
10564 |
0 |
0 |
T63 |
5036 |
74 |
0 |
0 |
T64 |
102558 |
1697 |
0 |
0 |
T93 |
10139 |
109 |
0 |
0 |
T98 |
11888 |
282 |
0 |
0 |
T100 |
90683 |
221 |
0 |
0 |
T105 |
4148 |
122 |
0 |
0 |
T115 |
3960 |
59 |
0 |
0 |
T127 |
14364 |
177 |
0 |
0 |
T128 |
7991 |
219 |
0 |
0 |
T129 |
14619 |
138 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
11298 |
0 |
0 |
T63 |
5036 |
85 |
0 |
0 |
T64 |
102558 |
2296 |
0 |
0 |
T93 |
10139 |
171 |
0 |
0 |
T98 |
11888 |
199 |
0 |
0 |
T100 |
90683 |
231 |
0 |
0 |
T105 |
4148 |
132 |
0 |
0 |
T115 |
3960 |
63 |
0 |
0 |
T127 |
14364 |
181 |
0 |
0 |
T128 |
7991 |
6 |
0 |
0 |
T129 |
14619 |
108 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
10010 |
0 |
0 |
T63 |
5036 |
72 |
0 |
0 |
T64 |
102558 |
2170 |
0 |
0 |
T93 |
10139 |
136 |
0 |
0 |
T98 |
11888 |
109 |
0 |
0 |
T100 |
90683 |
202 |
0 |
0 |
T107 |
180348 |
387 |
0 |
0 |
T127 |
14364 |
165 |
0 |
0 |
T128 |
7991 |
131 |
0 |
0 |
T129 |
14619 |
133 |
0 |
0 |
T130 |
19558 |
52 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
11173 |
0 |
0 |
T63 |
5036 |
85 |
0 |
0 |
T64 |
102558 |
1639 |
0 |
0 |
T93 |
10139 |
262 |
0 |
0 |
T98 |
11888 |
270 |
0 |
0 |
T100 |
90683 |
192 |
0 |
0 |
T105 |
4148 |
102 |
0 |
0 |
T115 |
3960 |
1 |
0 |
0 |
T127 |
14364 |
176 |
0 |
0 |
T128 |
7991 |
136 |
0 |
0 |
T129 |
14619 |
85 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
9871 |
0 |
0 |
T63 |
5036 |
2 |
0 |
0 |
T64 |
102558 |
1874 |
0 |
0 |
T93 |
10139 |
26 |
0 |
0 |
T98 |
11888 |
254 |
0 |
0 |
T100 |
90683 |
218 |
0 |
0 |
T115 |
3960 |
38 |
0 |
0 |
T127 |
14364 |
155 |
0 |
0 |
T128 |
7991 |
119 |
0 |
0 |
T129 |
14619 |
161 |
0 |
0 |
T130 |
19558 |
35 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
5048 |
0 |
0 |
T64 |
102558 |
627 |
0 |
0 |
T93 |
10139 |
105 |
0 |
0 |
T98 |
11888 |
83 |
0 |
0 |
T100 |
90683 |
247 |
0 |
0 |
T105 |
4148 |
61 |
0 |
0 |
T115 |
3960 |
32 |
0 |
0 |
T127 |
14364 |
45 |
0 |
0 |
T128 |
7991 |
83 |
0 |
0 |
T129 |
14619 |
36 |
0 |
0 |
T130 |
19558 |
20 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
5804 |
0 |
0 |
T64 |
102558 |
871 |
0 |
0 |
T93 |
10139 |
102 |
0 |
0 |
T98 |
11888 |
166 |
0 |
0 |
T100 |
90683 |
233 |
0 |
0 |
T105 |
4148 |
26 |
0 |
0 |
T115 |
3960 |
6 |
0 |
0 |
T127 |
14364 |
26 |
0 |
0 |
T128 |
7991 |
102 |
0 |
0 |
T129 |
14619 |
89 |
0 |
0 |
T130 |
19558 |
72 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
5508 |
0 |
0 |
T63 |
5036 |
41 |
0 |
0 |
T64 |
102558 |
739 |
0 |
0 |
T93 |
10139 |
17 |
0 |
0 |
T98 |
11888 |
59 |
0 |
0 |
T100 |
90683 |
226 |
0 |
0 |
T105 |
4148 |
40 |
0 |
0 |
T127 |
14364 |
40 |
0 |
0 |
T128 |
7991 |
7 |
0 |
0 |
T129 |
14619 |
49 |
0 |
0 |
T130 |
19558 |
50 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
5374 |
0 |
0 |
T63 |
5036 |
55 |
0 |
0 |
T64 |
102558 |
688 |
0 |
0 |
T93 |
10139 |
61 |
0 |
0 |
T98 |
11888 |
51 |
0 |
0 |
T100 |
90683 |
222 |
0 |
0 |
T105 |
4148 |
39 |
0 |
0 |
T115 |
3960 |
7 |
0 |
0 |
T127 |
14364 |
33 |
0 |
0 |
T128 |
7991 |
47 |
0 |
0 |
T130 |
19558 |
88 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
4880 |
0 |
0 |
T64 |
102558 |
611 |
0 |
0 |
T93 |
10139 |
119 |
0 |
0 |
T98 |
11888 |
121 |
0 |
0 |
T100 |
90683 |
220 |
0 |
0 |
T105 |
4148 |
4 |
0 |
0 |
T115 |
3960 |
30 |
0 |
0 |
T127 |
14364 |
75 |
0 |
0 |
T128 |
7991 |
96 |
0 |
0 |
T129 |
14619 |
18 |
0 |
0 |
T130 |
19558 |
54 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
5132 |
0 |
0 |
T64 |
102558 |
727 |
0 |
0 |
T93 |
10139 |
99 |
0 |
0 |
T98 |
11888 |
58 |
0 |
0 |
T100 |
90683 |
165 |
0 |
0 |
T105 |
4148 |
1 |
0 |
0 |
T107 |
180348 |
481 |
0 |
0 |
T127 |
14364 |
13 |
0 |
0 |
T128 |
7991 |
62 |
0 |
0 |
T129 |
14619 |
112 |
0 |
0 |
T130 |
19558 |
32 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
5702 |
0 |
0 |
T63 |
5036 |
42 |
0 |
0 |
T64 |
102558 |
1114 |
0 |
0 |
T93 |
10139 |
50 |
0 |
0 |
T98 |
11888 |
101 |
0 |
0 |
T100 |
90683 |
252 |
0 |
0 |
T105 |
4148 |
7 |
0 |
0 |
T115 |
3960 |
24 |
0 |
0 |
T127 |
14364 |
60 |
0 |
0 |
T128 |
7991 |
66 |
0 |
0 |
T129 |
14619 |
107 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
5339 |
0 |
0 |
T63 |
5036 |
25 |
0 |
0 |
T64 |
102558 |
857 |
0 |
0 |
T93 |
10139 |
62 |
0 |
0 |
T98 |
11888 |
9 |
0 |
0 |
T100 |
90683 |
249 |
0 |
0 |
T105 |
4148 |
66 |
0 |
0 |
T127 |
14364 |
34 |
0 |
0 |
T128 |
7991 |
50 |
0 |
0 |
T129 |
14619 |
48 |
0 |
0 |
T130 |
19558 |
47 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
5218 |
0 |
0 |
T63 |
5036 |
22 |
0 |
0 |
T64 |
102558 |
588 |
0 |
0 |
T93 |
10139 |
19 |
0 |
0 |
T98 |
11888 |
39 |
0 |
0 |
T100 |
90683 |
206 |
0 |
0 |
T105 |
4148 |
4 |
0 |
0 |
T115 |
3960 |
7 |
0 |
0 |
T127 |
14364 |
24 |
0 |
0 |
T128 |
7991 |
38 |
0 |
0 |
T129 |
14619 |
73 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
4969 |
0 |
0 |
T63 |
5036 |
5 |
0 |
0 |
T64 |
102558 |
747 |
0 |
0 |
T93 |
10139 |
105 |
0 |
0 |
T98 |
11888 |
14 |
0 |
0 |
T100 |
90683 |
209 |
0 |
0 |
T105 |
4148 |
51 |
0 |
0 |
T115 |
3960 |
26 |
0 |
0 |
T127 |
14364 |
28 |
0 |
0 |
T128 |
7991 |
69 |
0 |
0 |
T129 |
14619 |
37 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
5689 |
0 |
0 |
T63 |
5036 |
27 |
0 |
0 |
T64 |
102558 |
752 |
0 |
0 |
T93 |
10139 |
55 |
0 |
0 |
T98 |
11888 |
87 |
0 |
0 |
T100 |
90683 |
207 |
0 |
0 |
T105 |
4148 |
53 |
0 |
0 |
T115 |
3960 |
8 |
0 |
0 |
T127 |
14364 |
41 |
0 |
0 |
T128 |
7991 |
68 |
0 |
0 |
T129 |
14619 |
47 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
5169 |
0 |
0 |
T63 |
5036 |
13 |
0 |
0 |
T64 |
102558 |
760 |
0 |
0 |
T93 |
10139 |
62 |
0 |
0 |
T98 |
11888 |
89 |
0 |
0 |
T100 |
90683 |
237 |
0 |
0 |
T115 |
3960 |
5 |
0 |
0 |
T127 |
14364 |
24 |
0 |
0 |
T128 |
7991 |
115 |
0 |
0 |
T129 |
14619 |
42 |
0 |
0 |
T130 |
19558 |
90 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
5698 |
0 |
0 |
T63 |
5036 |
46 |
0 |
0 |
T64 |
102558 |
995 |
0 |
0 |
T93 |
10139 |
50 |
0 |
0 |
T98 |
11888 |
105 |
0 |
0 |
T100 |
90683 |
229 |
0 |
0 |
T105 |
4148 |
1 |
0 |
0 |
T115 |
3960 |
17 |
0 |
0 |
T127 |
14364 |
19 |
0 |
0 |
T128 |
7991 |
102 |
0 |
0 |
T129 |
14619 |
37 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
5285 |
0 |
0 |
T63 |
5036 |
10 |
0 |
0 |
T64 |
102558 |
730 |
0 |
0 |
T93 |
10139 |
8 |
0 |
0 |
T98 |
11888 |
143 |
0 |
0 |
T100 |
90683 |
233 |
0 |
0 |
T105 |
4148 |
9 |
0 |
0 |
T115 |
3960 |
16 |
0 |
0 |
T127 |
14364 |
72 |
0 |
0 |
T128 |
7991 |
50 |
0 |
0 |
T129 |
14619 |
35 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
5575 |
0 |
0 |
T63 |
5036 |
10 |
0 |
0 |
T64 |
102558 |
678 |
0 |
0 |
T85 |
13373 |
1 |
0 |
0 |
T93 |
10139 |
87 |
0 |
0 |
T98 |
11888 |
155 |
0 |
0 |
T100 |
90683 |
221 |
0 |
0 |
T105 |
4148 |
47 |
0 |
0 |
T115 |
3960 |
3 |
0 |
0 |
T127 |
14364 |
111 |
0 |
0 |
T128 |
7991 |
58 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
5094 |
0 |
0 |
T63 |
5036 |
7 |
0 |
0 |
T64 |
102558 |
885 |
0 |
0 |
T93 |
10139 |
132 |
0 |
0 |
T98 |
11888 |
102 |
0 |
0 |
T100 |
90683 |
229 |
0 |
0 |
T105 |
4148 |
23 |
0 |
0 |
T115 |
3960 |
19 |
0 |
0 |
T127 |
14364 |
11 |
0 |
0 |
T128 |
7991 |
98 |
0 |
0 |
T129 |
14619 |
25 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
5470 |
0 |
0 |
T63 |
5036 |
10 |
0 |
0 |
T64 |
102558 |
913 |
0 |
0 |
T93 |
10139 |
42 |
0 |
0 |
T98 |
11888 |
146 |
0 |
0 |
T100 |
90683 |
213 |
0 |
0 |
T105 |
4148 |
44 |
0 |
0 |
T115 |
3960 |
2 |
0 |
0 |
T127 |
14364 |
47 |
0 |
0 |
T128 |
7991 |
10 |
0 |
0 |
T129 |
14619 |
43 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
5725 |
0 |
0 |
T63 |
5036 |
7 |
0 |
0 |
T64 |
102558 |
770 |
0 |
0 |
T93 |
10139 |
13 |
0 |
0 |
T98 |
11888 |
18 |
0 |
0 |
T100 |
90683 |
223 |
0 |
0 |
T105 |
4148 |
63 |
0 |
0 |
T115 |
3960 |
5 |
0 |
0 |
T127 |
14364 |
62 |
0 |
0 |
T128 |
7991 |
11 |
0 |
0 |
T129 |
14619 |
46 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
5431 |
0 |
0 |
T63 |
5036 |
22 |
0 |
0 |
T64 |
102558 |
651 |
0 |
0 |
T93 |
10139 |
128 |
0 |
0 |
T98 |
11888 |
46 |
0 |
0 |
T100 |
90683 |
232 |
0 |
0 |
T105 |
4148 |
6 |
0 |
0 |
T127 |
14364 |
31 |
0 |
0 |
T128 |
7991 |
49 |
0 |
0 |
T129 |
14619 |
35 |
0 |
0 |
T130 |
19558 |
72 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
5741 |
0 |
0 |
T63 |
5036 |
25 |
0 |
0 |
T64 |
102558 |
816 |
0 |
0 |
T93 |
10139 |
10 |
0 |
0 |
T98 |
11888 |
18 |
0 |
0 |
T100 |
90683 |
227 |
0 |
0 |
T105 |
4148 |
9 |
0 |
0 |
T115 |
3960 |
5 |
0 |
0 |
T127 |
14364 |
120 |
0 |
0 |
T128 |
7991 |
12 |
0 |
0 |
T129 |
14619 |
57 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
5154 |
0 |
0 |
T63 |
5036 |
1 |
0 |
0 |
T64 |
102558 |
734 |
0 |
0 |
T93 |
10139 |
21 |
0 |
0 |
T98 |
11888 |
114 |
0 |
0 |
T100 |
90683 |
220 |
0 |
0 |
T105 |
4148 |
46 |
0 |
0 |
T115 |
3960 |
20 |
0 |
0 |
T127 |
14364 |
39 |
0 |
0 |
T128 |
7991 |
52 |
0 |
0 |
T129 |
14619 |
61 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
5600 |
0 |
0 |
T63 |
5036 |
1 |
0 |
0 |
T64 |
102558 |
661 |
0 |
0 |
T84 |
19410 |
10 |
0 |
0 |
T93 |
10139 |
60 |
0 |
0 |
T98 |
11888 |
8 |
0 |
0 |
T100 |
90683 |
196 |
0 |
0 |
T105 |
4148 |
55 |
0 |
0 |
T115 |
3960 |
2 |
0 |
0 |
T127 |
14364 |
58 |
0 |
0 |
T128 |
7991 |
2 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
5155 |
0 |
0 |
T63 |
5036 |
29 |
0 |
0 |
T64 |
102558 |
632 |
0 |
0 |
T85 |
13373 |
5 |
0 |
0 |
T93 |
10139 |
59 |
0 |
0 |
T98 |
11888 |
84 |
0 |
0 |
T100 |
90683 |
210 |
0 |
0 |
T105 |
4148 |
35 |
0 |
0 |
T127 |
14364 |
11 |
0 |
0 |
T128 |
7991 |
116 |
0 |
0 |
T129 |
14619 |
11 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
6046 |
0 |
0 |
T63 |
5036 |
30 |
0 |
0 |
T64 |
102558 |
834 |
0 |
0 |
T84 |
19410 |
5 |
0 |
0 |
T93 |
10139 |
138 |
0 |
0 |
T98 |
11888 |
123 |
0 |
0 |
T100 |
90683 |
210 |
0 |
0 |
T105 |
4148 |
47 |
0 |
0 |
T115 |
3960 |
16 |
0 |
0 |
T127 |
14364 |
50 |
0 |
0 |
T128 |
7991 |
2 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
2776 |
0 |
0 |
T63 |
5036 |
12 |
0 |
0 |
T64 |
102558 |
207 |
0 |
0 |
T93 |
10139 |
46 |
0 |
0 |
T98 |
11888 |
5 |
0 |
0 |
T100 |
90683 |
254 |
0 |
0 |
T105 |
4148 |
7 |
0 |
0 |
T127 |
14364 |
27 |
0 |
0 |
T128 |
7991 |
15 |
0 |
0 |
T129 |
14619 |
7 |
0 |
0 |
T130 |
19558 |
120 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
2647 |
0 |
0 |
T63 |
5036 |
9 |
0 |
0 |
T64 |
102558 |
148 |
0 |
0 |
T84 |
19410 |
7 |
0 |
0 |
T93 |
10139 |
14 |
0 |
0 |
T98 |
11888 |
13 |
0 |
0 |
T100 |
90683 |
206 |
0 |
0 |
T105 |
4148 |
8 |
0 |
0 |
T115 |
3960 |
6 |
0 |
0 |
T127 |
14364 |
11 |
0 |
0 |
T128 |
7991 |
19 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
2529 |
0 |
0 |
T63 |
5036 |
11 |
0 |
0 |
T64 |
102558 |
158 |
0 |
0 |
T82 |
11940 |
3 |
0 |
0 |
T93 |
10139 |
20 |
0 |
0 |
T98 |
11888 |
14 |
0 |
0 |
T100 |
90683 |
239 |
0 |
0 |
T105 |
4148 |
5 |
0 |
0 |
T127 |
14364 |
7 |
0 |
0 |
T128 |
7991 |
7 |
0 |
0 |
T129 |
14619 |
4 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
2513 |
0 |
0 |
T63 |
5036 |
7 |
0 |
0 |
T64 |
102558 |
153 |
0 |
0 |
T93 |
10139 |
22 |
0 |
0 |
T98 |
11888 |
6 |
0 |
0 |
T100 |
90683 |
212 |
0 |
0 |
T115 |
3960 |
2 |
0 |
0 |
T127 |
14364 |
7 |
0 |
0 |
T128 |
7991 |
20 |
0 |
0 |
T129 |
14619 |
14 |
0 |
0 |
T130 |
19558 |
77 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
2982 |
0 |
0 |
T63 |
5036 |
2 |
0 |
0 |
T64 |
102558 |
249 |
0 |
0 |
T93 |
10139 |
20 |
0 |
0 |
T98 |
11888 |
16 |
0 |
0 |
T100 |
90683 |
193 |
0 |
0 |
T105 |
4148 |
1 |
0 |
0 |
T115 |
3960 |
6 |
0 |
0 |
T127 |
14364 |
24 |
0 |
0 |
T128 |
7991 |
18 |
0 |
0 |
T129 |
14619 |
7 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
5125 |
0 |
0 |
T26 |
350646 |
40 |
0 |
0 |
T27 |
0 |
39 |
0 |
0 |
T29 |
0 |
33 |
0 |
0 |
T30 |
0 |
30 |
0 |
0 |
T43 |
623544 |
0 |
0 |
0 |
T44 |
589785 |
0 |
0 |
0 |
T45 |
395895 |
0 |
0 |
0 |
T80 |
366266 |
0 |
0 |
0 |
T96 |
41125 |
0 |
0 |
0 |
T97 |
10439 |
0 |
0 |
0 |
T131 |
0 |
34 |
0 |
0 |
T132 |
0 |
33 |
0 |
0 |
T133 |
0 |
12 |
0 |
0 |
T134 |
0 |
37 |
0 |
0 |
T135 |
0 |
81 |
0 |
0 |
T136 |
0 |
18 |
0 |
0 |
T137 |
2248 |
0 |
0 |
0 |
T138 |
803741 |
0 |
0 |
0 |
T139 |
105181 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
2646 |
0 |
0 |
T63 |
5036 |
5 |
0 |
0 |
T64 |
102558 |
169 |
0 |
0 |
T93 |
10139 |
15 |
0 |
0 |
T98 |
11888 |
17 |
0 |
0 |
T100 |
90683 |
215 |
0 |
0 |
T105 |
4148 |
10 |
0 |
0 |
T115 |
3960 |
4 |
0 |
0 |
T127 |
14364 |
1 |
0 |
0 |
T128 |
7991 |
3 |
0 |
0 |
T129 |
14619 |
19 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
2522 |
0 |
0 |
T63 |
5036 |
2 |
0 |
0 |
T64 |
102558 |
214 |
0 |
0 |
T93 |
10139 |
22 |
0 |
0 |
T98 |
11888 |
11 |
0 |
0 |
T100 |
90683 |
227 |
0 |
0 |
T105 |
4148 |
8 |
0 |
0 |
T115 |
3960 |
2 |
0 |
0 |
T127 |
14364 |
15 |
0 |
0 |
T128 |
7991 |
14 |
0 |
0 |
T129 |
14619 |
7 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
2355 |
0 |
0 |
T64 |
102558 |
105 |
0 |
0 |
T93 |
10139 |
19 |
0 |
0 |
T98 |
11888 |
9 |
0 |
0 |
T100 |
90683 |
209 |
0 |
0 |
T105 |
4148 |
5 |
0 |
0 |
T107 |
180348 |
478 |
0 |
0 |
T127 |
14364 |
14 |
0 |
0 |
T128 |
7991 |
10 |
0 |
0 |
T129 |
14619 |
12 |
0 |
0 |
T130 |
19558 |
72 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
2327 |
0 |
0 |
T63 |
5036 |
2 |
0 |
0 |
T64 |
102558 |
124 |
0 |
0 |
T93 |
10139 |
13 |
0 |
0 |
T98 |
11888 |
12 |
0 |
0 |
T100 |
90683 |
205 |
0 |
0 |
T107 |
180348 |
419 |
0 |
0 |
T127 |
14364 |
13 |
0 |
0 |
T128 |
7991 |
11 |
0 |
0 |
T129 |
14619 |
8 |
0 |
0 |
T130 |
19558 |
88 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
2357 |
0 |
0 |
T63 |
5036 |
3 |
0 |
0 |
T64 |
102558 |
88 |
0 |
0 |
T93 |
10139 |
12 |
0 |
0 |
T98 |
11888 |
13 |
0 |
0 |
T100 |
90683 |
236 |
0 |
0 |
T105 |
4148 |
7 |
0 |
0 |
T127 |
14364 |
12 |
0 |
0 |
T128 |
7991 |
7 |
0 |
0 |
T129 |
14619 |
4 |
0 |
0 |
T130 |
19558 |
69 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
2260 |
0 |
0 |
T63 |
5036 |
8 |
0 |
0 |
T64 |
102558 |
90 |
0 |
0 |
T93 |
10139 |
15 |
0 |
0 |
T98 |
11888 |
22 |
0 |
0 |
T100 |
90683 |
187 |
0 |
0 |
T105 |
4148 |
7 |
0 |
0 |
T127 |
14364 |
10 |
0 |
0 |
T128 |
7991 |
8 |
0 |
0 |
T129 |
14619 |
18 |
0 |
0 |
T130 |
19558 |
50 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
3163 |
0 |
0 |
T64 |
102558 |
291 |
0 |
0 |
T93 |
10139 |
31 |
0 |
0 |
T98 |
11888 |
32 |
0 |
0 |
T100 |
90683 |
190 |
0 |
0 |
T105 |
4148 |
13 |
0 |
0 |
T115 |
3960 |
3 |
0 |
0 |
T127 |
14364 |
7 |
0 |
0 |
T128 |
7991 |
32 |
0 |
0 |
T129 |
14619 |
14 |
0 |
0 |
T130 |
19558 |
75 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
2219 |
0 |
0 |
T64 |
102558 |
126 |
0 |
0 |
T85 |
13373 |
7 |
0 |
0 |
T93 |
10139 |
13 |
0 |
0 |
T98 |
11888 |
26 |
0 |
0 |
T100 |
90683 |
184 |
0 |
0 |
T105 |
4148 |
4 |
0 |
0 |
T127 |
14364 |
4 |
0 |
0 |
T128 |
7991 |
1 |
0 |
0 |
T129 |
14619 |
18 |
0 |
0 |
T130 |
19558 |
38 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
3543 |
0 |
0 |
T63 |
5036 |
6 |
0 |
0 |
T64 |
102558 |
285 |
0 |
0 |
T93 |
10139 |
25 |
0 |
0 |
T98 |
11888 |
21 |
0 |
0 |
T100 |
90683 |
227 |
0 |
0 |
T105 |
4148 |
24 |
0 |
0 |
T115 |
3960 |
7 |
0 |
0 |
T127 |
14364 |
27 |
0 |
0 |
T128 |
7991 |
24 |
0 |
0 |
T129 |
14619 |
15 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
2613 |
0 |
0 |
T63 |
5036 |
8 |
0 |
0 |
T64 |
102558 |
195 |
0 |
0 |
T93 |
10139 |
20 |
0 |
0 |
T98 |
11888 |
25 |
0 |
0 |
T100 |
90683 |
236 |
0 |
0 |
T105 |
4148 |
8 |
0 |
0 |
T115 |
3960 |
9 |
0 |
0 |
T127 |
14364 |
8 |
0 |
0 |
T128 |
7991 |
14 |
0 |
0 |
T129 |
14619 |
8 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
2333 |
0 |
0 |
T63 |
5036 |
8 |
0 |
0 |
T64 |
102558 |
141 |
0 |
0 |
T93 |
10139 |
18 |
0 |
0 |
T98 |
11888 |
7 |
0 |
0 |
T100 |
90683 |
207 |
0 |
0 |
T105 |
4148 |
4 |
0 |
0 |
T127 |
14364 |
7 |
0 |
0 |
T128 |
7991 |
8 |
0 |
0 |
T129 |
14619 |
23 |
0 |
0 |
T130 |
19558 |
49 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
2457 |
0 |
0 |
T63 |
5036 |
4 |
0 |
0 |
T64 |
102558 |
141 |
0 |
0 |
T93 |
10139 |
23 |
0 |
0 |
T98 |
11888 |
10 |
0 |
0 |
T100 |
90683 |
232 |
0 |
0 |
T105 |
4148 |
2 |
0 |
0 |
T115 |
3960 |
6 |
0 |
0 |
T127 |
14364 |
21 |
0 |
0 |
T128 |
7991 |
15 |
0 |
0 |
T129 |
14619 |
22 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
2309 |
0 |
0 |
T63 |
5036 |
12 |
0 |
0 |
T64 |
102558 |
127 |
0 |
0 |
T93 |
10139 |
20 |
0 |
0 |
T98 |
11888 |
7 |
0 |
0 |
T100 |
90683 |
224 |
0 |
0 |
T105 |
4148 |
1 |
0 |
0 |
T127 |
14364 |
24 |
0 |
0 |
T128 |
7991 |
12 |
0 |
0 |
T129 |
14619 |
7 |
0 |
0 |
T130 |
19558 |
67 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
2304 |
0 |
0 |
T63 |
5036 |
9 |
0 |
0 |
T64 |
102558 |
116 |
0 |
0 |
T93 |
10139 |
17 |
0 |
0 |
T98 |
11888 |
11 |
0 |
0 |
T100 |
90683 |
230 |
0 |
0 |
T105 |
4148 |
2 |
0 |
0 |
T127 |
14364 |
12 |
0 |
0 |
T128 |
7991 |
2 |
0 |
0 |
T129 |
14619 |
5 |
0 |
0 |
T130 |
19558 |
88 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
2395 |
0 |
0 |
T63 |
5036 |
2 |
0 |
0 |
T64 |
102558 |
125 |
0 |
0 |
T93 |
10139 |
14 |
0 |
0 |
T98 |
11888 |
2 |
0 |
0 |
T100 |
90683 |
258 |
0 |
0 |
T105 |
4148 |
3 |
0 |
0 |
T115 |
3960 |
5 |
0 |
0 |
T127 |
14364 |
14 |
0 |
0 |
T128 |
7991 |
16 |
0 |
0 |
T129 |
14619 |
31 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480072078 |
2265 |
0 |
0 |
T64 |
102558 |
111 |
0 |
0 |
T93 |
10139 |
16 |
0 |
0 |
T98 |
11888 |
14 |
0 |
0 |
T100 |
90683 |
194 |
0 |
0 |
T105 |
4148 |
10 |
0 |
0 |
T107 |
180348 |
436 |
0 |
0 |
T127 |
14364 |
28 |
0 |
0 |
T128 |
7991 |
11 |
0 |
0 |
T129 |
14619 |
8 |
0 |
0 |
T130 |
19558 |
30 |
0 |
0 |