Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3375548	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4177381

1

T1

81

T2

14089

T3

109

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4068593	1			T1	1790		T2	5285		T3	149
values[0x0]	1741409	1			T1	31		T2	5734		T3	49
values[0x1]	1742927	1			T1	37		T2	5698		T3	51

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2397324	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5155605

1

T1

691

T2

14607

T3

149

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	32191	1			T2	70		T5	34		T7	21
valid_sources[0x01]	28350	1			T2	68		T5	40		T7	22
valid_sources[0x02]	26117	1			T2	39		T5	31		T7	21
valid_sources[0x03]	30934	1			T2	54		T5	32		T7	33
valid_sources[0x04]	30634	1			T2	80		T5	54		T7	19
valid_sources[0x05]	27940	1			T2	68		T5	38		T7	22
valid_sources[0x06]	29413	1			T2	69		T5	46		T7	22
valid_sources[0x07]	30073	1			T2	68		T5	45		T7	25
valid_sources[0x08]	30677	1			T2	46		T5	44		T7	20
valid_sources[0x09]	30205	1			T2	59		T5	28		T7	26
valid_sources[0x0a]	27254	1			T2	75		T5	40		T7	27
valid_sources[0x0b]	28411	1			T2	85		T5	38		T7	21
valid_sources[0x0c]	27949	1			T2	65		T5	48		T7	26
valid_sources[0x0d]	28336	1			T2	45		T5	47		T7	35
valid_sources[0x0e]	28716	1			T2	74		T5	63		T7	32
valid_sources[0x0f]	25871	1			T2	85		T5	36		T7	37
valid_sources[0x10]	30480	1			T2	46		T5	36		T7	38
valid_sources[0x11]	29251	1			T2	65		T5	40		T7	26
valid_sources[0x12]	28241	1			T2	67		T5	46		T7	28
valid_sources[0x13]	26470	1			T2	64		T5	35		T7	23
valid_sources[0x14]	39108	1			T2	64		T5	29		T7	32
valid_sources[0x15]	31421	1			T2	44		T5	46		T7	23
valid_sources[0x16]	31322	1			T2	94		T5	33		T7	21
valid_sources[0x17]	27014	1			T2	72		T5	31		T7	21
valid_sources[0x18]	30941	1			T2	63		T5	25		T7	19
valid_sources[0x19]	29764	1			T2	44		T5	48		T7	27
valid_sources[0x1a]	38216	1			T2	72		T5	50		T7	30
valid_sources[0x1b]	31143	1			T2	68		T5	45		T7	27
valid_sources[0x1c]	29876	1			T2	63		T5	36		T7	32
valid_sources[0x1d]	26794	1			T2	59		T5	40		T7	16
valid_sources[0x1e]	27395	1			T2	78		T5	39		T7	30
valid_sources[0x1f]	30096	1			T2	78		T5	46		T7	20
valid_sources[0x20]	27806	1			T2	65		T5	37		T7	34
valid_sources[0x21]	27604	1			T2	83		T5	37		T7	26
valid_sources[0x22]	27450	1			T2	60		T4	894		T5	38
valid_sources[0x23]	28779	1			T2	85		T5	37		T7	22
valid_sources[0x24]	33568	1			T2	79		T5	30		T7	35
valid_sources[0x25]	28549	1			T2	69		T5	48		T7	20
valid_sources[0x26]	28737	1			T2	48		T5	39		T7	31
valid_sources[0x27]	26233	1			T2	81		T5	42		T7	23
valid_sources[0x28]	29695	1			T2	72		T5	39		T7	28
valid_sources[0x29]	29609	1			T2	60		T5	44		T7	32
valid_sources[0x2a]	27951	1			T2	57		T5	55		T7	27
valid_sources[0x2b]	27168	1			T2	69		T5	34		T7	29
valid_sources[0x2c]	36358	1			T2	64		T5	35		T7	18
valid_sources[0x2d]	27173	1			T2	80		T5	42		T7	42
valid_sources[0x2e]	27421	1			T2	49		T5	40		T7	30
valid_sources[0x2f]	35995	1			T2	62		T5	47		T7	34
valid_sources[0x30]	31074	1			T2	55		T5	29		T7	25
valid_sources[0x31]	27660	1			T2	49		T5	39		T7	38
valid_sources[0x32]	27469	1			T2	52		T5	34		T7	33
valid_sources[0x33]	26785	1			T2	46		T5	50		T7	25
valid_sources[0x34]	29536	1			T2	80		T5	42		T7	33
valid_sources[0x35]	29554	1			T2	77		T5	48		T7	29
valid_sources[0x36]	28220	1			T2	58		T5	55		T7	23
valid_sources[0x37]	27755	1			T2	56		T5	37		T7	37
valid_sources[0x38]	37267	1			T2	45		T5	42		T7	28
valid_sources[0x39]	27658	1			T2	71		T5	39		T7	29
valid_sources[0x3a]	29898	1			T2	75		T5	52		T7	34
valid_sources[0x3b]	26919	1			T2	62		T5	35		T7	29
valid_sources[0x3c]	28408	1			T2	38		T5	51		T7	17
valid_sources[0x3d]	27486	1			T2	46		T5	36		T7	32
valid_sources[0x3e]	26448	1			T2	69		T5	44		T7	31
valid_sources[0x3f]	28037	1			T2	56		T5	43		T7	16
valid_sources[0x40]	33591	1			T2	59		T5	30		T7	27
valid_sources[0x41]	26903	1			T2	57		T5	28		T7	28
valid_sources[0x42]	36851	1			T2	54		T5	33		T7	22
valid_sources[0x43]	29621	1			T2	55		T5	48		T7	27
valid_sources[0x44]	31288	1			T2	67		T5	62		T7	27
valid_sources[0x45]	28297	1			T2	54		T5	33		T7	18
valid_sources[0x46]	29211	1			T2	61		T5	36		T7	25
valid_sources[0x47]	26694	1			T2	74		T5	33		T7	37
valid_sources[0x48]	30148	1			T2	49		T5	42		T7	34
valid_sources[0x49]	28600	1			T2	59		T5	50		T7	38
valid_sources[0x4a]	27831	1			T2	69		T5	54		T7	25
valid_sources[0x4b]	29256	1			T2	41		T5	46		T7	26
valid_sources[0x4c]	29033	1			T2	54		T5	37		T7	25
valid_sources[0x4d]	29404	1			T2	56		T4	452		T5	52
valid_sources[0x4e]	32127	1			T2	59		T5	39		T7	18
valid_sources[0x4f]	30784	1			T2	76		T5	35		T7	26
valid_sources[0x50]	28227	1			T2	55		T5	49		T7	31
valid_sources[0x51]	27123	1			T2	65		T5	47		T7	31
valid_sources[0x52]	29686	1			T2	88		T5	58		T7	28
valid_sources[0x53]	26780	1			T2	63		T5	41		T7	25
valid_sources[0x54]	25994	1			T2	74		T5	41		T7	27
valid_sources[0x55]	39860	1			T2	61		T5	43		T7	26
valid_sources[0x56]	29620	1			T2	70		T5	41		T7	24
valid_sources[0x57]	28278	1			T2	71		T5	38		T7	35
valid_sources[0x58]	29430	1			T2	57		T5	34		T7	23
valid_sources[0x59]	28712	1			T2	64		T5	39		T7	20
valid_sources[0x5a]	29049	1			T2	69		T5	55		T7	19
valid_sources[0x5b]	32739	1			T2	64		T5	45		T7	25
valid_sources[0x5c]	27539	1			T2	69		T5	55		T7	30
valid_sources[0x5d]	28801	1			T2	80		T5	47		T7	19
valid_sources[0x5e]	26903	1			T2	59		T5	30		T7	23
valid_sources[0x5f]	29813	1			T2	65		T5	42		T7	15
valid_sources[0x60]	35990	1			T2	68		T5	48		T7	23
valid_sources[0x61]	28399	1			T2	75		T5	49		T7	24
valid_sources[0x62]	30127	1			T2	79		T5	44		T7	40
valid_sources[0x63]	33517	1			T2	73		T5	47		T7	31
valid_sources[0x64]	28600	1			T2	53		T5	48		T7	28
valid_sources[0x65]	27850	1			T2	68		T5	31		T7	21
valid_sources[0x66]	27422	1			T2	75		T5	37		T7	21
valid_sources[0x67]	34795	1			T2	69		T5	59		T7	24
valid_sources[0x68]	28822	1			T2	59		T5	45		T7	33
valid_sources[0x69]	31487	1			T2	58		T5	40		T7	28
valid_sources[0x6a]	26093	1			T2	62		T5	48		T7	28
valid_sources[0x6b]	27779	1			T2	90		T5	45		T7	33
valid_sources[0x6c]	28748	1			T2	59		T5	40		T7	28
valid_sources[0x6d]	28451	1			T2	70		T5	33		T7	35
valid_sources[0x6e]	27152	1			T2	82		T5	43		T7	22
valid_sources[0x6f]	26467	1			T2	59		T5	44		T7	35
valid_sources[0x70]	28917	1			T2	52		T5	47		T7	32
valid_sources[0x71]	27898	1			T2	69		T5	37		T7	31
valid_sources[0x72]	27487	1			T2	103		T5	46		T7	21
valid_sources[0x73]	27557	1			T2	65		T5	32		T7	31
valid_sources[0x74]	29426	1			T2	67		T5	35		T7	23
valid_sources[0x75]	27771	1			T2	94		T5	42		T7	45
valid_sources[0x76]	34606	1			T2	57		T5	47		T7	24
valid_sources[0x77]	26656	1			T2	60		T5	44		T7	16
valid_sources[0x78]	30340	1			T2	79		T5	40		T7	31
valid_sources[0x79]	26771	1			T2	55		T5	44		T7	28
valid_sources[0x7a]	29130	1			T2	50		T5	41		T7	26
valid_sources[0x7b]	29794	1			T2	71		T5	50		T7	22
valid_sources[0x7c]	30300	1			T2	55		T5	42		T7	23
valid_sources[0x7d]	38093	1			T2	56		T5	44		T6	8773
valid_sources[0x7e]	30643	1			T2	76		T5	44		T7	31
valid_sources[0x7f]	27020	1			T2	67		T5	41		T7	27
valid_sources[0x80]	31563	1			T2	52		T5	39		T7	27

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1006890

1

T1

52

T2

2705

T3

33

values[0x0]

all_enables

biggest_size

1597103

1

T1

15

T2

5715

T3

35

values[0x1]

all_enables

biggest_size

1573388

1

T1

14

T2

5669

T3

41