Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3396584

1

T1

1777

T2

2628

T3

140

full_word

4178526

1

T1

81

T2

14089

T3

109

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7574700	1			T1	1858		T2	16717		T3	249
auto[TlIntgErrCmd]	139	1			T72	5		T104	3		T105	8
auto[TlIntgErrData]	131	1			T72	9		T104	4		T105	9
auto[TlIntgErrBoth]	140	1			T72	6		T104	3		T105	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4072150

1

T1

1790

T2

5285

T3

149

auto[1]

3502960

1

T1

68

T2

11432

T3

100

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3064814	1			T1	1738		T2	2580		T3	116
auto[TlIntgErrNone]	partial	auto[1]	331386	1			T1	39		T2	48		T3	24
auto[TlIntgErrNone]	full_word	auto[0]	1007149	1			T1	52		T2	2705		T3	33
auto[TlIntgErrNone]	full_word	auto[1]	3171351	1			T1	29		T2	11384		T3	76
auto[TlIntgErrCmd]	partial	auto[0]	58	1			T72	3		T105	1		T183	1
auto[TlIntgErrCmd]	partial	auto[1]	73	1			T72	2		T104	3		T105	6
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T185	1		T186	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T105	1		T187	2		T188	1
auto[TlIntgErrData]	partial	auto[0]	55	1			T72	4		T104	3		T105	4
auto[TlIntgErrData]	partial	auto[1]	67	1			T72	5		T104	1		T105	4
auto[TlIntgErrData]	full_word	auto[0]	6	1			T183	1		T189	1		T190	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T105	1		T166	1		T184	1
auto[TlIntgErrBoth]	partial	auto[0]	60	1			T72	4		T104	1		T166	2
auto[TlIntgErrBoth]	partial	auto[1]	71	1			T72	2		T104	2		T105	3
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T185	1		T187	2		T188	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T166	1		T189	1		T187	1