Unified Coverage Report :: Module :: prim_pulse_sync

Module : prim_pulse_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_readbuf_watermark_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_flash_readbuf_flip_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_upload.u_payloadptr_clr_psync	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_upload.u_payloadptr_clr_psync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.37	100.00	86.11		100.00	95.74	100.00	u_upload

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T7
1	0	Covered	T2,T5,T7
1	1	Covered	T2,T5,T8

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T7
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T5,T7

---

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1377418893	2901	0	0
SrcPulseCheck_M	448706316	2901	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1377418893	2901	0	0
T2	328994	8	0	0
T3	5682	0	0	0
T5	0	7	0	0
T7	0	1	0	0
T8	0	2	0	0
T10	0	15	0	0
T12	0	5	0	0
T14	0	5	0	0
T15	381699	0	0	0
T37	22320	1	0	0
T38	64747	0	0	0
T43	0	8	0	0
T44	0	4	0	0
T46	470320	7	0	0
T47	0	7	0	0
T48	0	7	0	0
T49	317437	0	0	0
T50	700328	0	0	0
T51	209102	0	0	0
T54	0	2	0	0
T62	75314	0	0	0
T63	784676	0	0	0
T80	0	7	0	0
T93	1912	0	0	0
T95	81278	0	0	0
T102	106267	0	0	0
T106	11473	0	0	0
T137	0	7	0	0
T150	0	7	0	0
T151	0	6	0	0
T152	0	7	0	0
T153	0	9	0	0
T154	0	7	0	0
T155	3485	0	0	0
T156	317387	0	0	0
T157	60918	0	0	0
T158	194474	0	0	0
T159	13862	0	0	0
T160	12892	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	448706316	2901	0	0
T2	107666	8	0	0
T3	4152	0	0	0
T5	0	7	0	0
T7	0	1	0	0
T8	0	2	0	0
T10	0	15	0	0
T12	0	5	0	0
T14	0	5	0	0
T15	798519	0	0	0
T37	17981	1	0	0
T38	111677	0	0	0
T43	0	8	0	0
T44	0	4	0	0
T46	58004	7	0	0
T47	0	7	0	0
T48	0	7	0	0
T49	62332	0	0	0
T50	98924	0	0	0
T51	550025	0	0	0
T54	0	2	0	0
T62	23371	0	0	0
T63	243355	0	0	0
T80	0	7	0	0
T93	216	0	0	0
T95	19536	0	0	0
T102	190290	0	0	0
T106	26009	0	0	0
T137	0	7	0	0
T150	0	7	0	0
T151	0	6	0	0
T152	0	7	0	0
T153	0	9	0	0
T154	0	7	0	0
T155	4548	0	0	0
T156	39404	0	0	0
T157	19116	0	0	0
T158	93213	0	0	0
T159	16902	0	0	0
T160	9680	0	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T37,T46,T47
1	0	Covered	T37,T46,T47
1	1	Covered	T46,T47,T48

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T37,T46,T47
1	0	Covered	T46,T47,T48
1	1	Covered	T37,T46,T47

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	459139631	186	0	0
SrcPulseCheck_M	149568772	186	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459139631	186	0	0
T37	22320	1	0	0
T38	64747	0	0	0
T46	235160	2	0	0
T47	0	2	0	0
T48	0	2	0	0
T49	317437	0	0	0
T50	700328	0	0	0
T51	209102	0	0	0
T80	0	2	0	0
T106	11473	0	0	0
T137	0	2	0	0
T150	0	2	0	0
T152	0	4	0	0
T153	0	5	0	0
T154	0	2	0	0
T155	3485	0	0	0
T156	317387	0	0	0
T157	60918	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	149568772	186	0	0
T37	17981	1	0	0
T38	111677	0	0	0
T46	29002	2	0	0
T47	0	2	0	0
T48	0	2	0	0
T49	62332	0	0	0
T50	98924	0	0	0
T51	550025	0	0	0
T80	0	2	0	0
T106	26009	0	0	0
T137	0	2	0	0
T150	0	2	0	0
T152	0	4	0	0
T153	0	5	0	0
T154	0	2	0	0
T155	4548	0	0	0
T156	39404	0	0	0
T157	19116	0	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T46,T47,T48
1	0	Covered	T46,T47,T48
1	1	Covered	T46,T47,T48

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T46,T47,T48
1	0	Covered	T46,T47,T48
1	1	Covered	T46,T47,T48

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	459139631	330	0	0
SrcPulseCheck_M	149568772	330	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459139631	330	0	0
T15	381699	0	0	0
T46	235160	5	0	0
T47	0	5	0	0
T48	0	5	0	0
T62	75314	0	0	0
T63	784676	0	0	0
T80	0	5	0	0
T93	1912	0	0	0
T95	81278	0	0	0
T102	106267	0	0	0
T137	0	5	0	0
T150	0	5	0	0
T151	0	6	0	0
T152	0	3	0	0
T153	0	4	0	0
T154	0	5	0	0
T158	194474	0	0	0
T159	13862	0	0	0
T160	12892	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	149568772	330	0	0
T15	798519	0	0	0
T46	29002	5	0	0
T47	0	5	0	0
T48	0	5	0	0
T62	23371	0	0	0
T63	243355	0	0	0
T80	0	5	0	0
T93	216	0	0	0
T95	19536	0	0	0
T102	190290	0	0	0
T137	0	5	0	0
T150	0	5	0	0
T151	0	6	0	0
T152	0	3	0	0
T153	0	4	0	0
T154	0	5	0	0
T158	93213	0	0	0
T159	16902	0	0	0
T160	9680	0	0	0

Line Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T7
1	0	Covered	T2,T5,T7
1	1	Covered	T2,T5,T8

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T7
1	0	Covered	T2,T5,T8
1	1	Covered	T2,T5,T7

---

Branch Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	459139631	2385	0	0
SrcPulseCheck_M	149568772	2385	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459139631	2385	0	0
T2	328994	8	0	0
T3	5682	0	0	0
T4	36280	0	0	0
T5	376933	7	0	0
T6	194150	0	0	0
T7	299419	1	0	0
T8	73751	2	0	0
T9	1258	0	0	0
T10	175633	15	0	0
T11	33061	0	0	0
T12	0	5	0	0
T14	0	5	0	0
T43	0	8	0	0
T44	0	4	0	0
T54	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	149568772	2385	0	0
T2	107666	8	0	0
T3	4152	0	0	0
T4	124233	0	0	0
T5	647392	7	0	0
T6	37337	0	0	0
T7	59728	1	0	0
T8	222833	2	0	0
T10	416384	15	0	0
T11	14544	0	0	0
T12	534863	5	0	0
T14	0	5	0	0
T43	0	8	0	0
T44	0	4	0	0
T54	0	2	0	0