Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Unreachable
1	1	Covered	T1,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T7
1	0	Covered	T2,T5,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Unreachable
1	1	Covered	T2,T5,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	758277175	607309414	0	0
CheckNGreaterZero_A	2868	2868	0	0
GntImpliesReady_A	758277175	3691337	0	0
GntImpliesValid_A	758277175	3691337	0	0
GrantKnown_A	758277175	607309414	0	0
IdxKnown_A	758277175	607309414	0	0
IndexIsCorrect_A	758277175	3691337	0	0
LockArbDecision_A	758277175	0	0	0
NoReadyValidNoGrant_A	758277175	0	0	0
ReadyAndValidImplyGrant_A	758277175	3691337	0	0
ReqAndReadyImplyGrant_A	758277175	3691337	0	0
ReqImpliesValid_A	758277175	3691337	0	0
ReqStaysHighUntilGranted0_M	758277175	0	0	0
RoundRobin_A	758277175	9	0	956
ValidKnown_A	758277175	607309414	0	0
gen_data_port_assertion.DataFlow_A	758277175	3691337	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758277175	607309414	0	0
T1	7640	7560	0	0
T2	544326	436417	0	0
T3	13986	9746	0	0
T4	284746	160264	0	0
T5	1671717	1021471	0	0
T6	268824	230645	0	0
T7	418875	358320	0	0
T8	519417	296233	0	0
T9	1258	1175	0	0
T10	1008401	587949	0	0
T11	29088	14544	0	0
T12	534863	533136	0	0
T13	0	11608	0	0
T29	0	10960	0	0
T30	0	153832	0	0
T32	0	3024	0	0
T33	0	864	0	0
T34	0	67512	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2868	2868	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758277175	3691337	0	0
T1	7640	260	0	0
T2	544326	11482	0	0
T3	13986	257	0	0
T4	284746	832	0	0
T5	1671717	9800	0	0
T6	268824	832	0	0
T7	418875	3228	0	0
T8	519417	2507	0	0
T9	1258	0	0	0
T10	1008401	14026	0	0
T11	29088	832	0	0
T12	534863	2443	0	0
T14	0	893	0	0
T22	0	258	0	0
T29	0	524	0	0
T30	0	5499	0	0
T32	0	192	0	0
T43	0	6823	0	0
T44	0	776	0	0
T54	0	514	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758277175	3691337	0	0
T1	7640	260	0	0
T2	544326	11482	0	0
T3	13986	257	0	0
T4	284746	832	0	0
T5	1671717	9800	0	0
T6	268824	832	0	0
T7	418875	3228	0	0
T8	519417	2507	0	0
T9	1258	0	0	0
T10	1008401	14026	0	0
T11	29088	832	0	0
T12	534863	2443	0	0
T14	0	893	0	0
T22	0	258	0	0
T29	0	524	0	0
T30	0	5499	0	0
T32	0	192	0	0
T43	0	6823	0	0
T44	0	776	0	0
T54	0	514	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758277175	607309414	0	0
T1	7640	7560	0	0
T2	544326	436417	0	0
T3	13986	9746	0	0
T4	284746	160264	0	0
T5	1671717	1021471	0	0
T6	268824	230645	0	0
T7	418875	358320	0	0
T8	519417	296233	0	0
T9	1258	1175	0	0
T10	1008401	587949	0	0
T11	29088	14544	0	0
T12	534863	533136	0	0
T13	0	11608	0	0
T29	0	10960	0	0
T30	0	153832	0	0
T32	0	3024	0	0
T33	0	864	0	0
T34	0	67512	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758277175	607309414	0	0
T1	7640	7560	0	0
T2	544326	436417	0	0
T3	13986	9746	0	0
T4	284746	160264	0	0
T5	1671717	1021471	0	0
T6	268824	230645	0	0
T7	418875	358320	0	0
T8	519417	296233	0	0
T9	1258	1175	0	0
T10	1008401	587949	0	0
T11	29088	14544	0	0
T12	534863	533136	0	0
T13	0	11608	0	0
T29	0	10960	0	0
T30	0	153832	0	0
T32	0	3024	0	0
T33	0	864	0	0
T34	0	67512	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758277175	3691337	0	0
T1	7640	260	0	0
T2	544326	11482	0	0
T3	13986	257	0	0
T4	284746	832	0	0
T5	1671717	9800	0	0
T6	268824	832	0	0
T7	418875	3228	0	0
T8	519417	2507	0	0
T9	1258	0	0	0
T10	1008401	14026	0	0
T11	29088	832	0	0
T12	534863	2443	0	0
T14	0	893	0	0
T22	0	258	0	0
T29	0	524	0	0
T30	0	5499	0	0
T32	0	192	0	0
T43	0	6823	0	0
T44	0	776	0	0
T54	0	514	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758277175	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758277175	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758277175	3691337	0	0
T1	7640	260	0	0
T2	544326	11482	0	0
T3	13986	257	0	0
T4	284746	832	0	0
T5	1671717	9800	0	0
T6	268824	832	0	0
T7	418875	3228	0	0
T8	519417	2507	0	0
T9	1258	0	0	0
T10	1008401	14026	0	0
T11	29088	832	0	0
T12	534863	2443	0	0
T14	0	893	0	0
T22	0	258	0	0
T29	0	524	0	0
T30	0	5499	0	0
T32	0	192	0	0
T43	0	6823	0	0
T44	0	776	0	0
T54	0	514	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758277175	3691337	0	0
T1	7640	260	0	0
T2	544326	11482	0	0
T3	13986	257	0	0
T4	284746	832	0	0
T5	1671717	9800	0	0
T6	268824	832	0	0
T7	418875	3228	0	0
T8	519417	2507	0	0
T9	1258	0	0	0
T10	1008401	14026	0	0
T11	29088	832	0	0
T12	534863	2443	0	0
T14	0	893	0	0
T22	0	258	0	0
T29	0	524	0	0
T30	0	5499	0	0
T32	0	192	0	0
T43	0	6823	0	0
T44	0	776	0	0
T54	0	514	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758277175	3691337	0	0
T1	7640	260	0	0
T2	544326	11482	0	0
T3	13986	257	0	0
T4	284746	832	0	0
T5	1671717	9800	0	0
T6	268824	832	0	0
T7	418875	3228	0	0
T8	519417	2507	0	0
T9	1258	0	0	0
T10	1008401	14026	0	0
T11	29088	832	0	0
T12	534863	2443	0	0
T14	0	893	0	0
T22	0	258	0	0
T29	0	524	0	0
T30	0	5499	0	0
T32	0	192	0	0
T43	0	6823	0	0
T44	0	776	0	0
T54	0	514	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	758277175	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758277175	9	0	956
T15	381699	1	0	1
T45	321556	0	0	1
T47	31902	0	0	1
T48	12618	0	0	1
T52	156703	0	0	1
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	2	0	0
T61	0	1	0	0
T62	75314	0	0	1
T63	784676	0	0	1
T64	349764	0	0	1
T65	105077	0	0	1
T66	1953	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758277175	607309414	0	0
T1	7640	7560	0	0
T2	544326	436417	0	0
T3	13986	9746	0	0
T4	284746	160264	0	0
T5	1671717	1021471	0	0
T6	268824	230645	0	0
T7	418875	358320	0	0
T8	519417	296233	0	0
T9	1258	1175	0	0
T10	1008401	587949	0	0
T11	29088	14544	0	0
T12	534863	533136	0	0
T13	0	11608	0	0
T29	0	10960	0	0
T30	0	153832	0	0
T32	0	3024	0	0
T33	0	864	0	0
T34	0	67512	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758277175	3691337	0	0
T1	7640	260	0	0
T2	544326	11482	0	0
T3	13986	257	0	0
T4	284746	832	0	0
T5	1671717	9800	0	0
T6	268824	832	0	0
T7	418875	3228	0	0
T8	519417	2507	0	0
T9	1258	0	0	0
T10	1008401	14026	0	0
T11	29088	832	0	0
T12	534863	2443	0	0
T14	0	893	0	0
T22	0	258	0	0
T29	0	524	0	0
T30	0	5499	0	0
T32	0	192	0	0
T43	0	6823	0	0
T44	0	776	0	0
T54	0	514	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Unreachable
1	1	Covered	T1,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T3,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	149568772	25758180	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	149568772	600762	0	0
GntImpliesValid_A	149568772	600762	0	0
GrantKnown_A	149568772	25758180	0	0
IdxKnown_A	149568772	25758180	0	0
IndexIsCorrect_A	149568772	600762	0	0
LockArbDecision_A	149568772	0	0	0
NoReadyValidNoGrant_A	149568772	0	0	0
ReadyAndValidImplyGrant_A	149568772	600762	0	0
ReqAndReadyImplyGrant_A	149568772	600762	0	0
ReqImpliesValid_A	149568772	600762	0	0
ReqStaysHighUntilGranted0_M	149568772	0	0	0
RoundRobin_A	149568772	0	0	0
ValidKnown_A	149568772	25758180	0	0
gen_data_port_assertion.DataFlow_A	149568772	600762	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149568772	25758180	0	0
T1	2176	2176	0	0
T2	107666	0	0	0
T3	4152	4152	0	0
T4	124233	0	0	0
T5	647392	51120	0	0
T6	37337	0	0	0
T7	59728	33880	0	0
T8	222833	0	0	0
T10	416384	0	0	0
T11	14544	0	0	0
T12	0	52600	0	0
T29	0	10960	0	0
T30	0	153832	0	0
T32	0	3024	0	0
T33	0	864	0	0
T34	0	67512	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149568772	600762	0	0
T1	2176	200	0	0
T2	107666	0	0	0
T3	4152	168	0	0
T4	124233	0	0	0
T5	647392	799	0	0
T6	37337	0	0	0
T7	59728	1617	0	0
T8	222833	0	0	0
T10	416384	0	0	0
T11	14544	0	0	0
T12	0	1534	0	0
T14	0	880	0	0
T22	0	258	0	0
T29	0	524	0	0
T30	0	5499	0	0
T32	0	192	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149568772	600762	0	0
T1	2176	200	0	0
T2	107666	0	0	0
T3	4152	168	0	0
T4	124233	0	0	0
T5	647392	799	0	0
T6	37337	0	0	0
T7	59728	1617	0	0
T8	222833	0	0	0
T10	416384	0	0	0
T11	14544	0	0	0
T12	0	1534	0	0
T14	0	880	0	0
T22	0	258	0	0
T29	0	524	0	0
T30	0	5499	0	0
T32	0	192	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149568772	25758180	0	0
T1	2176	2176	0	0
T2	107666	0	0	0
T3	4152	4152	0	0
T4	124233	0	0	0
T5	647392	51120	0	0
T6	37337	0	0	0
T7	59728	33880	0	0
T8	222833	0	0	0
T10	416384	0	0	0
T11	14544	0	0	0
T12	0	52600	0	0
T29	0	10960	0	0
T30	0	153832	0	0
T32	0	3024	0	0
T33	0	864	0	0
T34	0	67512	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149568772	25758180	0	0
T1	2176	2176	0	0
T2	107666	0	0	0
T3	4152	4152	0	0
T4	124233	0	0	0
T5	647392	51120	0	0
T6	37337	0	0	0
T7	59728	33880	0	0
T8	222833	0	0	0
T10	416384	0	0	0
T11	14544	0	0	0
T12	0	52600	0	0
T29	0	10960	0	0
T30	0	153832	0	0
T32	0	3024	0	0
T33	0	864	0	0
T34	0	67512	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149568772	600762	0	0
T1	2176	200	0	0
T2	107666	0	0	0
T3	4152	168	0	0
T4	124233	0	0	0
T5	647392	799	0	0
T6	37337	0	0	0
T7	59728	1617	0	0
T8	222833	0	0	0
T10	416384	0	0	0
T11	14544	0	0	0
T12	0	1534	0	0
T14	0	880	0	0
T22	0	258	0	0
T29	0	524	0	0
T30	0	5499	0	0
T32	0	192	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149568772	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149568772	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149568772	600762	0	0
T1	2176	200	0	0
T2	107666	0	0	0
T3	4152	168	0	0
T4	124233	0	0	0
T5	647392	799	0	0
T6	37337	0	0	0
T7	59728	1617	0	0
T8	222833	0	0	0
T10	416384	0	0	0
T11	14544	0	0	0
T12	0	1534	0	0
T14	0	880	0	0
T22	0	258	0	0
T29	0	524	0	0
T30	0	5499	0	0
T32	0	192	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149568772	600762	0	0
T1	2176	200	0	0
T2	107666	0	0	0
T3	4152	168	0	0
T4	124233	0	0	0
T5	647392	799	0	0
T6	37337	0	0	0
T7	59728	1617	0	0
T8	222833	0	0	0
T10	416384	0	0	0
T11	14544	0	0	0
T12	0	1534	0	0
T14	0	880	0	0
T22	0	258	0	0
T29	0	524	0	0
T30	0	5499	0	0
T32	0	192	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149568772	600762	0	0
T1	2176	200	0	0
T2	107666	0	0	0
T3	4152	168	0	0
T4	124233	0	0	0
T5	647392	799	0	0
T6	37337	0	0	0
T7	59728	1617	0	0
T8	222833	0	0	0
T10	416384	0	0	0
T11	14544	0	0	0
T12	0	1534	0	0
T14	0	880	0	0
T22	0	258	0	0
T29	0	524	0	0
T30	0	5499	0	0
T32	0	192	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	149568772	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149568772	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149568772	25758180	0	0
T1	2176	2176	0	0
T2	107666	0	0	0
T3	4152	4152	0	0
T4	124233	0	0	0
T5	647392	51120	0	0
T6	37337	0	0	0
T7	59728	33880	0	0
T8	222833	0	0	0
T10	416384	0	0	0
T11	14544	0	0	0
T12	0	52600	0	0
T29	0	10960	0	0
T30	0	153832	0	0
T32	0	3024	0	0
T33	0	864	0	0
T34	0	67512	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149568772	600762	0	0
T1	2176	200	0	0
T2	107666	0	0	0
T3	4152	168	0	0
T4	124233	0	0	0
T5	647392	799	0	0
T6	37337	0	0	0
T7	59728	1617	0	0
T8	222833	0	0	0
T10	416384	0	0	0
T11	14544	0	0	0
T12	0	1534	0	0
T14	0	880	0	0
T22	0	258	0	0
T29	0	524	0	0
T30	0	5499	0	0
T32	0	192	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T7
1	0	Covered	T2,T5,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Unreachable
1	1	Covered	T2,T5,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T5,T7
0	0	1	Unreachable
0	0	0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	149568772	122500049	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	149568772	794904	0	0
GntImpliesValid_A	149568772	794904	0	0
GrantKnown_A	149568772	122500049	0	0
IdxKnown_A	149568772	122500049	0	0
IndexIsCorrect_A	149568772	794904	0	0
LockArbDecision_A	149568772	0	0	0
NoReadyValidNoGrant_A	149568772	0	0	0
ReadyAndValidImplyGrant_A	149568772	794904	0	0
ReqAndReadyImplyGrant_A	149568772	794904	0	0
ReqImpliesValid_A	149568772	794904	0	0
ReqStaysHighUntilGranted0_M	149568772	0	0	0
RoundRobin_A	149568772	0	0	0
ValidKnown_A	149568772	122500049	0	0
gen_data_port_assertion.DataFlow_A	149568772	794904	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149568772	122500049	0	0
T2	107666	107430	0	0
T3	4152	0	0	0
T4	124233	124082	0	0
T5	647392	593477	0	0
T6	37337	36592	0	0
T7	59728	25090	0	0
T8	222833	222564	0	0
T10	416384	412324	0	0
T11	14544	14544	0	0
T12	534863	480536	0	0
T13	0	11608	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149568772	794904	0	0
T2	107666	525	0	0
T3	4152	0	0	0
T4	124233	0	0	0
T5	647392	1046	0	0
T6	37337	0	0	0
T7	59728	4	0	0
T8	222833	7	0	0
T10	416384	5204	0	0
T11	14544	0	0	0
T12	534863	909	0	0
T14	0	13	0	0
T43	0	6823	0	0
T44	0	776	0	0
T54	0	514	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149568772	794904	0	0
T2	107666	525	0	0
T3	4152	0	0	0
T4	124233	0	0	0
T5	647392	1046	0	0
T6	37337	0	0	0
T7	59728	4	0	0
T8	222833	7	0	0
T10	416384	5204	0	0
T11	14544	0	0	0
T12	534863	909	0	0
T14	0	13	0	0
T43	0	6823	0	0
T44	0	776	0	0
T54	0	514	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149568772	122500049	0	0
T2	107666	107430	0	0
T3	4152	0	0	0
T4	124233	124082	0	0
T5	647392	593477	0	0
T6	37337	36592	0	0
T7	59728	25090	0	0
T8	222833	222564	0	0
T10	416384	412324	0	0
T11	14544	14544	0	0
T12	534863	480536	0	0
T13	0	11608	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149568772	122500049	0	0
T2	107666	107430	0	0
T3	4152	0	0	0
T4	124233	124082	0	0
T5	647392	593477	0	0
T6	37337	36592	0	0
T7	59728	25090	0	0
T8	222833	222564	0	0
T10	416384	412324	0	0
T11	14544	14544	0	0
T12	534863	480536	0	0
T13	0	11608	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149568772	794904	0	0
T2	107666	525	0	0
T3	4152	0	0	0
T4	124233	0	0	0
T5	647392	1046	0	0
T6	37337	0	0	0
T7	59728	4	0	0
T8	222833	7	0	0
T10	416384	5204	0	0
T11	14544	0	0	0
T12	534863	909	0	0
T14	0	13	0	0
T43	0	6823	0	0
T44	0	776	0	0
T54	0	514	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149568772	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149568772	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149568772	794904	0	0
T2	107666	525	0	0
T3	4152	0	0	0
T4	124233	0	0	0
T5	647392	1046	0	0
T6	37337	0	0	0
T7	59728	4	0	0
T8	222833	7	0	0
T10	416384	5204	0	0
T11	14544	0	0	0
T12	534863	909	0	0
T14	0	13	0	0
T43	0	6823	0	0
T44	0	776	0	0
T54	0	514	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149568772	794904	0	0
T2	107666	525	0	0
T3	4152	0	0	0
T4	124233	0	0	0
T5	647392	1046	0	0
T6	37337	0	0	0
T7	59728	4	0	0
T8	222833	7	0	0
T10	416384	5204	0	0
T11	14544	0	0	0
T12	534863	909	0	0
T14	0	13	0	0
T43	0	6823	0	0
T44	0	776	0	0
T54	0	514	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149568772	794904	0	0
T2	107666	525	0	0
T3	4152	0	0	0
T4	124233	0	0	0
T5	647392	1046	0	0
T6	37337	0	0	0
T7	59728	4	0	0
T8	222833	7	0	0
T10	416384	5204	0	0
T11	14544	0	0	0
T12	534863	909	0	0
T14	0	13	0	0
T43	0	6823	0	0
T44	0	776	0	0
T54	0	514	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	149568772	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149568772	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149568772	122500049	0	0
T2	107666	107430	0	0
T3	4152	0	0	0
T4	124233	124082	0	0
T5	647392	593477	0	0
T6	37337	36592	0	0
T7	59728	25090	0	0
T8	222833	222564	0	0
T10	416384	412324	0	0
T11	14544	14544	0	0
T12	534863	480536	0	0
T13	0	11608	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149568772	794904	0	0
T2	107666	525	0	0
T3	4152	0	0	0
T4	124233	0	0	0
T5	647392	1046	0	0
T6	37337	0	0	0
T7	59728	4	0	0
T8	222833	7	0	0
T10	416384	5204	0	0
T11	14544	0	0	0
T12	534863	909	0	0
T14	0	13	0	0
T43	0	6823	0	0
T44	0	776	0	0
T54	0	514	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	459139631	459051185	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	459139631	2295671	0	0
GntImpliesValid_A	459139631	2295671	0	0
GrantKnown_A	459139631	459051185	0	0
IdxKnown_A	459139631	459051185	0	0
IndexIsCorrect_A	459139631	2295671	0	0
LockArbDecision_A	459139631	0	0	0
NoReadyValidNoGrant_A	459139631	0	0	0
ReadyAndValidImplyGrant_A	459139631	2295671	0	0
ReqAndReadyImplyGrant_A	459139631	2295671	0	0
ReqImpliesValid_A	459139631	2295671	0	0
ReqStaysHighUntilGranted0_M	459139631	0	0	0
RoundRobin_A	459139631	9	0	956
ValidKnown_A	459139631	459051185	0	0
gen_data_port_assertion.DataFlow_A	459139631	2295671	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459139631	459051185	0	0
T1	5464	5384	0	0
T2	328994	328987	0	0
T3	5682	5594	0	0
T4	36280	36182	0	0
T5	376933	376874	0	0
T6	194150	194053	0	0
T7	299419	299350	0	0
T8	73751	73669	0	0
T9	1258	1175	0	0
T10	175633	175625	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459139631	2295671	0	0
T1	5464	60	0	0
T2	328994	10957	0	0
T3	5682	89	0	0
T4	36280	832	0	0
T5	376933	7955	0	0
T6	194150	832	0	0
T7	299419	1607	0	0
T8	73751	2500	0	0
T9	1258	0	0	0
T10	175633	8822	0	0
T11	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459139631	2295671	0	0
T1	5464	60	0	0
T2	328994	10957	0	0
T3	5682	89	0	0
T4	36280	832	0	0
T5	376933	7955	0	0
T6	194150	832	0	0
T7	299419	1607	0	0
T8	73751	2500	0	0
T9	1258	0	0	0
T10	175633	8822	0	0
T11	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459139631	459051185	0	0
T1	5464	5384	0	0
T2	328994	328987	0	0
T3	5682	5594	0	0
T4	36280	36182	0	0
T5	376933	376874	0	0
T6	194150	194053	0	0
T7	299419	299350	0	0
T8	73751	73669	0	0
T9	1258	1175	0	0
T10	175633	175625	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459139631	459051185	0	0
T1	5464	5384	0	0
T2	328994	328987	0	0
T3	5682	5594	0	0
T4	36280	36182	0	0
T5	376933	376874	0	0
T6	194150	194053	0	0
T7	299419	299350	0	0
T8	73751	73669	0	0
T9	1258	1175	0	0
T10	175633	175625	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459139631	2295671	0	0
T1	5464	60	0	0
T2	328994	10957	0	0
T3	5682	89	0	0
T4	36280	832	0	0
T5	376933	7955	0	0
T6	194150	832	0	0
T7	299419	1607	0	0
T8	73751	2500	0	0
T9	1258	0	0	0
T10	175633	8822	0	0
T11	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459139631	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459139631	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459139631	2295671	0	0
T1	5464	60	0	0
T2	328994	10957	0	0
T3	5682	89	0	0
T4	36280	832	0	0
T5	376933	7955	0	0
T6	194150	832	0	0
T7	299419	1607	0	0
T8	73751	2500	0	0
T9	1258	0	0	0
T10	175633	8822	0	0
T11	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459139631	2295671	0	0
T1	5464	60	0	0
T2	328994	10957	0	0
T3	5682	89	0	0
T4	36280	832	0	0
T5	376933	7955	0	0
T6	194150	832	0	0
T7	299419	1607	0	0
T8	73751	2500	0	0
T9	1258	0	0	0
T10	175633	8822	0	0
T11	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459139631	2295671	0	0
T1	5464	60	0	0
T2	328994	10957	0	0
T3	5682	89	0	0
T4	36280	832	0	0
T5	376933	7955	0	0
T6	194150	832	0	0
T7	299419	1607	0	0
T8	73751	2500	0	0
T9	1258	0	0	0
T10	175633	8822	0	0
T11	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	459139631	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459139631	9	0	956
T15	381699	1	0	1
T45	321556	0	0	1
T47	31902	0	0	1
T48	12618	0	0	1
T52	156703	0	0	1
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	2	0	0
T61	0	1	0	0
T62	75314	0	0	1
T63	784676	0	0	1
T64	349764	0	0	1
T65	105077	0	0	1
T66	1953	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459139631	459051185	0	0
T1	5464	5384	0	0
T2	328994	328987	0	0
T3	5682	5594	0	0
T4	36280	36182	0	0
T5	376933	376874	0	0
T6	194150	194053	0	0
T7	299419	299350	0	0
T8	73751	73669	0	0
T9	1258	1175	0	0
T10	175633	175625	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459139631	2295671	0	0
T1	5464	60	0	0
T2	328994	10957	0	0
T3	5682	89	0	0
T4	36280	832	0	0
T5	376933	7955	0	0
T6	194150	832	0	0
T7	299419	1607	0	0
T8	73751	2500	0	0
T9	1258	0	0	0
T10	175633	8822	0	0
T11	0	832	0	0