Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3628121	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4266404

1

T1

5644

T2

14643

T3

8560

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4372317	1			T1	2916		T2	15674		T3	2448
values[0x0]	1760509	1			T1	2731		T2	7421		T3	3459
values[0x1]	1761699	1			T1	2636		T2	7419		T3	3599

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2577571	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5316954

1

T1

6396

T2

19524

T3

8766

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	31790	1			T1	99		T2	113		T5	66
valid_sources[0x01]	30867	1			T1	5		T2	114		T3	202
valid_sources[0x02]	38337	1			T2	117		T3	78		T4	7
valid_sources[0x03]	29383	1			T1	130		T2	114		T3	92
valid_sources[0x04]	30103	1			T1	6		T2	117		T3	14
valid_sources[0x05]	30364	1			T1	16		T2	106		T3	110
valid_sources[0x06]	40059	1			T2	123		T5	56		T9	24
valid_sources[0x07]	32768	1			T1	48		T2	130		T3	34
valid_sources[0x08]	28730	1			T1	62		T2	118		T3	34
valid_sources[0x09]	27568	1			T1	10		T2	101		T3	27
valid_sources[0x0a]	30395	1			T1	8		T2	125		T3	31
valid_sources[0x0b]	29886	1			T1	3		T2	127		T4	3
valid_sources[0x0c]	26996	1			T1	1		T2	97		T3	9
valid_sources[0x0d]	33195	1			T1	6		T2	116		T4	6
valid_sources[0x0e]	33228	1			T1	2		T2	121		T3	25
valid_sources[0x0f]	30993	1			T2	103		T3	53		T5	59
valid_sources[0x10]	27541	1			T1	49		T2	100		T4	13
valid_sources[0x11]	27489	1			T1	51		T2	107		T5	50
valid_sources[0x12]	31150	1			T1	3		T2	101		T3	86
valid_sources[0x13]	28847	1			T1	60		T2	119		T3	271
valid_sources[0x14]	28194	1			T1	5		T2	106		T3	263
valid_sources[0x15]	30724	1			T2	142		T4	1		T5	52
valid_sources[0x16]	33503	1			T1	217		T2	104		T3	121
valid_sources[0x17]	31784	1			T1	9		T2	135		T3	15
valid_sources[0x18]	28783	1			T1	2		T2	124		T3	16
valid_sources[0x19]	30350	1			T1	4		T2	110		T3	8
valid_sources[0x1a]	33274	1			T1	67		T2	116		T3	180
valid_sources[0x1b]	30627	1			T1	2		T2	125		T5	67
valid_sources[0x1c]	30587	1			T1	2		T2	117		T4	13
valid_sources[0x1d]	31982	1			T1	97		T2	133		T3	4
valid_sources[0x1e]	31668	1			T1	48		T2	114		T4	11
valid_sources[0x1f]	29617	1			T2	102		T3	89		T4	31
valid_sources[0x20]	31074	1			T1	73		T2	128		T5	47
valid_sources[0x21]	29793	1			T1	24		T2	105		T3	48
valid_sources[0x22]	35982	1			T1	37		T2	100		T3	26
valid_sources[0x23]	29951	1			T2	130		T3	5		T4	3
valid_sources[0x24]	28101	1			T2	142		T3	1		T5	56
valid_sources[0x25]	27693	1			T1	17		T2	119		T4	18
valid_sources[0x26]	27468	1			T1	27		T2	111		T3	47
valid_sources[0x27]	28999	1			T2	120		T3	26		T5	37
valid_sources[0x28]	32984	1			T1	1		T2	112		T4	11
valid_sources[0x29]	35331	1			T1	11		T2	116		T3	20
valid_sources[0x2a]	30513	1			T2	131		T3	128		T4	6
valid_sources[0x2b]	25829	1			T2	114		T5	36		T9	34
valid_sources[0x2c]	35418	1			T2	110		T4	8		T5	44
valid_sources[0x2d]	30155	1			T1	4		T2	117		T3	26
valid_sources[0x2e]	43132	1			T1	21		T2	132		T3	17
valid_sources[0x2f]	30025	1			T1	14		T2	123		T3	2
valid_sources[0x30]	31089	1			T1	16		T2	89		T3	170
valid_sources[0x31]	28197	1			T2	112		T3	26		T4	7
valid_sources[0x32]	32221	1			T1	7		T2	133		T5	58
valid_sources[0x33]	30413	1			T1	1		T2	135		T3	143
valid_sources[0x34]	29048	1			T1	62		T2	111		T3	22
valid_sources[0x35]	27918	1			T1	1		T2	109		T3	29
valid_sources[0x36]	26826	1			T1	18		T2	119		T3	46
valid_sources[0x37]	27608	1			T1	4		T2	132		T5	66
valid_sources[0x38]	39419	1			T1	61		T2	111		T5	59
valid_sources[0x39]	32408	1			T1	47		T2	122		T4	1
valid_sources[0x3a]	28791	1			T1	49		T2	129		T3	16
valid_sources[0x3b]	25760	1			T2	118		T3	5		T5	64
valid_sources[0x3c]	27617	1			T1	22		T2	126		T3	25
valid_sources[0x3d]	32917	1			T1	20		T2	97		T3	27
valid_sources[0x3e]	31858	1			T1	14		T2	132		T3	39
valid_sources[0x3f]	28033	1			T1	7		T2	128		T4	1
valid_sources[0x40]	26280	1			T1	7		T2	104		T3	162
valid_sources[0x41]	27584	1			T1	5		T2	106		T4	8
valid_sources[0x42]	30209	1			T1	20		T2	116		T4	8
valid_sources[0x43]	33411	1			T2	112		T3	180		T4	14
valid_sources[0x44]	31375	1			T1	90		T2	126		T3	43
valid_sources[0x45]	30352	1			T2	109		T4	14		T5	58
valid_sources[0x46]	29563	1			T1	3		T2	115		T3	28
valid_sources[0x47]	28180	1			T2	127		T4	6		T5	65
valid_sources[0x48]	30605	1			T1	42		T2	109		T4	4
valid_sources[0x49]	33066	1			T1	15		T2	126		T3	35
valid_sources[0x4a]	34660	1			T1	2		T2	123		T3	414
valid_sources[0x4b]	32367	1			T1	23		T2	123		T3	38
valid_sources[0x4c]	29770	1			T1	1		T2	125		T3	147
valid_sources[0x4d]	32016	1			T2	127		T3	38		T4	18
valid_sources[0x4e]	30877	1			T1	4		T2	120		T3	66
valid_sources[0x4f]	27949	1			T1	111		T2	123		T3	31
valid_sources[0x50]	38439	1			T1	13		T2	105		T3	2
valid_sources[0x51]	30331	1			T1	20		T2	108		T3	11
valid_sources[0x52]	32946	1			T1	74		T2	131		T5	91
valid_sources[0x53]	33468	1			T2	106		T3	102		T4	20
valid_sources[0x54]	28247	1			T1	7		T2	136		T3	74
valid_sources[0x55]	30151	1			T1	87		T2	120		T4	3
valid_sources[0x56]	36713	1			T1	22		T2	105		T3	134
valid_sources[0x57]	26631	1			T1	2		T2	100		T3	176
valid_sources[0x58]	32968	1			T2	87		T3	95		T4	11
valid_sources[0x59]	29633	1			T1	31		T2	145		T3	13
valid_sources[0x5a]	28536	1			T1	102		T2	130		T3	28
valid_sources[0x5b]	29639	1			T1	84		T2	118		T3	43
valid_sources[0x5c]	33295	1			T1	5		T2	118		T3	35
valid_sources[0x5d]	30311	1			T1	8		T2	120		T3	65
valid_sources[0x5e]	26202	1			T1	14		T2	109		T4	7
valid_sources[0x5f]	26105	1			T1	14		T2	93		T5	77
valid_sources[0x60]	27739	1			T1	23		T2	117		T3	50
valid_sources[0x61]	27458	1			T1	19		T2	124		T4	1
valid_sources[0x62]	29351	1			T1	105		T2	118		T4	8
valid_sources[0x63]	35157	1			T1	4		T2	137		T5	27
valid_sources[0x64]	81737	1			T1	79		T2	111		T5	41
valid_sources[0x65]	32030	1			T1	80		T2	121		T4	22
valid_sources[0x66]	28027	1			T1	82		T2	112		T3	1
valid_sources[0x67]	31350	1			T1	66		T2	123		T4	16
valid_sources[0x68]	27502	1			T1	49		T2	128		T5	61
valid_sources[0x69]	30939	1			T1	127		T2	118		T3	10
valid_sources[0x6a]	32088	1			T2	91		T4	3		T5	67
valid_sources[0x6b]	27823	1			T1	15		T2	128		T4	5
valid_sources[0x6c]	29920	1			T1	4		T2	126		T4	14
valid_sources[0x6d]	27868	1			T1	17		T2	118		T3	12
valid_sources[0x6e]	33576	1			T2	78		T5	60		T8	1
valid_sources[0x6f]	29183	1			T1	128		T2	132		T3	1
valid_sources[0x70]	30786	1			T1	1		T2	119		T3	80
valid_sources[0x71]	37961	1			T1	83		T2	111		T4	8
valid_sources[0x72]	27373	1			T1	33		T2	117		T4	2
valid_sources[0x73]	26297	1			T1	62		T2	131		T4	3
valid_sources[0x74]	28786	1			T1	3		T2	112		T5	49
valid_sources[0x75]	29757	1			T1	155		T2	120		T4	27
valid_sources[0x76]	29186	1			T1	5		T2	124		T3	1
valid_sources[0x77]	27474	1			T1	30		T2	138		T3	7
valid_sources[0x78]	28436	1			T1	14		T2	122		T4	8
valid_sources[0x79]	30122	1			T1	145		T2	107		T4	34
valid_sources[0x7a]	39453	1			T1	4		T2	120		T3	110
valid_sources[0x7b]	32756	1			T1	3		T2	122		T3	32
valid_sources[0x7c]	30591	1			T1	60		T2	129		T3	2
valid_sources[0x7d]	30193	1			T1	91		T2	119		T3	1
valid_sources[0x7e]	29347	1			T2	124		T3	65		T5	44
valid_sources[0x7f]	29701	1			T1	35		T2	134		T4	1
valid_sources[0x80]	26720	1			T2	113		T4	9		T5	48

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1077889

1

T1

834

T2

1896

T3

1554

values[0x0]

all_enables

biggest_size

1606515

1

T1

2478

T2

6470

T3

3448

values[0x1]

all_enables

biggest_size

1582000

1

T1

2332

T2

6277

T3

3558