Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3649472

1

T1

2639

T2

15871

T3

946

full_word

4267595

1

T1

5644

T2

14643

T3

8560

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7916647	1			T1	8283		T2	30514		T3	9506
auto[TlIntgErrCmd]	140	1			T63	10		T64	6		T96	6
auto[TlIntgErrData]	142	1			T63	6		T64	11		T96	9
auto[TlIntgErrBoth]	138	1			T63	14		T64	3		T96	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4375497

1

T1

2916

T2

15674

T3

2448

auto[1]

3541570

1

T1

5367

T2

14840

T3

7058

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3297202	1			T1	2082		T2	13778		T3	894
auto[TlIntgErrNone]	partial	auto[1]	351883	1			T1	557		T2	2093		T3	52
auto[TlIntgErrNone]	full_word	auto[0]	1078124	1			T1	834		T2	1896		T3	1554
auto[TlIntgErrNone]	full_word	auto[1]	3189438	1			T1	4810		T2	12747		T3	7006
auto[TlIntgErrCmd]	partial	auto[0]	48	1			T63	1		T64	5		T96	3
auto[TlIntgErrCmd]	partial	auto[1]	80	1			T63	7		T64	1		T96	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T107	1		T171	1		T172	1
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T63	2		T106	1		T107	2
auto[TlIntgErrData]	partial	auto[0]	65	1			T63	4		T64	2		T96	4
auto[TlIntgErrData]	partial	auto[1]	67	1			T63	1		T64	7		T96	3
auto[TlIntgErrData]	full_word	auto[0]	3	1			T169	1		T170	1		T173	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T63	1		T64	2		T96	2
auto[TlIntgErrBoth]	partial	auto[0]	46	1			T63	6		T96	1		T106	2
auto[TlIntgErrBoth]	partial	auto[1]	81	1			T63	6		T64	3		T96	4
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T63	1		T106	1		T105	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T63	1		T108	1		T170	1