Unified Coverage Report :: Module :: prim_generic_ram_1r1w

Module : prim_generic_ram_1r1w

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1r1w

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	636003935	3340055	0	0
gen_wmask[1].MaskCheckPortA_A	636003935	3340055	0	0
gen_wmask[2].MaskCheckPortA_A	636003935	3340055	0	0
gen_wmask[3].MaskCheckPortA_A	636003935	3340055	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	636003935	3340055	0	0
T1	377944	8230	0	0
T2	490262	14266	0	0
T3	1276162	14383	0	0
T4	347765	832	0	0
T5	1017407	16334	0	0
T6	1369	0	0	0
T7	38671	832	0	0
T8	505680	4495	0	0
T9	412224	832	0	0
T10	3645	43	0	0
T11	25677	832	0	0
T13	0	8914	0	0
T25	0	237	0	0
T27	0	8310	0	0
T38	0	2734	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	636003935	3340055	0	0
T1	377944	8230	0	0
T2	490262	14266	0	0
T3	1276162	14383	0	0
T4	347765	832	0	0
T5	1017407	16334	0	0
T6	1369	0	0	0
T7	38671	832	0	0
T8	505680	4495	0	0
T9	412224	832	0	0
T10	3645	43	0	0
T11	25677	832	0	0
T13	0	8914	0	0
T25	0	237	0	0
T27	0	8310	0	0
T38	0	2734	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	636003935	3340055	0	0
T1	377944	8230	0	0
T2	490262	14266	0	0
T3	1276162	14383	0	0
T4	347765	832	0	0
T5	1017407	16334	0	0
T6	1369	0	0	0
T7	38671	832	0	0
T8	505680	4495	0	0
T9	412224	832	0	0
T10	3645	43	0	0
T11	25677	832	0	0
T13	0	8914	0	0
T25	0	237	0	0
T27	0	8310	0	0
T38	0	2734	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	636003935	3340055	0	0
T1	377944	8230	0	0
T2	490262	14266	0	0
T3	1276162	14383	0	0
T4	347765	832	0	0
T5	1017407	16334	0	0
T6	1369	0	0	0
T7	38671	832	0	0
T8	505680	4495	0	0
T9	412224	832	0	0
T10	3645	43	0	0
T11	25677	832	0	0
T13	0	8914	0	0
T25	0	237	0	0
T27	0	8310	0	0
T38	0	2734	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			==> MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	485729829	2077633	0	0
gen_wmask[1].MaskCheckPortA_A	485729829	2077633	0	0
gen_wmask[2].MaskCheckPortA_A	485729829	2077633	0	0
gen_wmask[3].MaskCheckPortA_A	485729829	2077633	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485729829	2077633	0	0
T1	194803	3833	0	0
T2	117406	7898	0	0
T3	966652	6656	0	0
T4	290427	832	0	0
T5	101845	10900	0	0
T6	1369	0	0	0
T7	34451	832	0	0
T8	148284	3160	0	0
T9	142344	832	0	0
T10	1773	42	0	0
T11	0	832	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485729829	2077633	0	0
T1	194803	3833	0	0
T2	117406	7898	0	0
T3	966652	6656	0	0
T4	290427	832	0	0
T5	101845	10900	0	0
T6	1369	0	0	0
T7	34451	832	0	0
T8	148284	3160	0	0
T9	142344	832	0	0
T10	1773	42	0	0
T11	0	832	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485729829	2077633	0	0
T1	194803	3833	0	0
T2	117406	7898	0	0
T3	966652	6656	0	0
T4	290427	832	0	0
T5	101845	10900	0	0
T6	1369	0	0	0
T7	34451	832	0	0
T8	148284	3160	0	0
T9	142344	832	0	0
T10	1773	42	0	0
T11	0	832	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485729829	2077633	0	0
T1	194803	3833	0	0
T2	117406	7898	0	0
T3	966652	6656	0	0
T4	290427	832	0	0
T5	101845	10900	0	0
T6	1369	0	0	0
T7	34451	832	0	0
T8	148284	3160	0	0
T9	142344	832	0	0
T10	1773	42	0	0
T11	0	832	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	150274106	1262422	0	0
gen_wmask[1].MaskCheckPortA_A	150274106	1262422	0	0
gen_wmask[2].MaskCheckPortA_A	150274106	1262422	0	0
gen_wmask[3].MaskCheckPortA_A	150274106	1262422	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150274106	1262422	0	0
T1	183141	4397	0	0
T2	372856	6368	0	0
T3	309510	7727	0	0
T4	57338	0	0	0
T5	915562	5434	0	0
T7	4220	0	0	0
T8	357396	1335	0	0
T9	269880	0	0	0
T10	1872	1	0	0
T11	25677	0	0	0
T13	0	8914	0	0
T25	0	237	0	0
T27	0	8310	0	0
T38	0	2734	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150274106	1262422	0	0
T1	183141	4397	0	0
T2	372856	6368	0	0
T3	309510	7727	0	0
T4	57338	0	0	0
T5	915562	5434	0	0
T7	4220	0	0	0
T8	357396	1335	0	0
T9	269880	0	0	0
T10	1872	1	0	0
T11	25677	0	0	0
T13	0	8914	0	0
T25	0	237	0	0
T27	0	8310	0	0
T38	0	2734	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150274106	1262422	0	0
T1	183141	4397	0	0
T2	372856	6368	0	0
T3	309510	7727	0	0
T4	57338	0	0	0
T5	915562	5434	0	0
T7	4220	0	0	0
T8	357396	1335	0	0
T9	269880	0	0	0
T10	1872	1	0	0
T11	25677	0	0	0
T13	0	8914	0	0
T25	0	237	0	0
T27	0	8310	0	0
T38	0	2734	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150274106	1262422	0	0
T1	183141	4397	0	0
T2	372856	6368	0	0
T3	309510	7727	0	0
T4	57338	0	0	0
T5	915562	5434	0	0
T7	4220	0	0	0
T8	357396	1335	0	0
T9	269880	0	0	0
T10	1872	1	0	0
T11	25677	0	0	0
T13	0	8914	0	0
T25	0	237	0	0
T27	0	8310	0	0
T38	0	2734	0	0