Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	488260216	2842507	0	0
DepthKnown_A	488260216	488125270	0	0
RvalidKnown_A	488260216	488125270	0	0
WreadyKnown_A	488260216	488125270	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488260216	2842507	0	0
T1	194803	4162	0	0
T2	117406	8317	0	0
T3	966652	9980	0	0
T4	290427	1663	0	0
T5	101845	14997	0	0
T6	1369	0	0	0
T7	34451	832	0	0
T8	148284	3327	0	0
T9	142344	832	0	0
T10	1773	0	0	0
T11	0	1663	0	0
T12	0	1663	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488260216	488125270	0	0
T1	194803	194742	0	0
T2	117406	117397	0	0
T3	966652	966576	0	0
T4	290427	290364	0	0
T5	101845	101837	0	0
T6	1369	1277	0	0
T7	34451	34359	0	0
T8	148284	148206	0	0
T9	142344	142273	0	0
T10	1773	1696	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488260216	488125270	0	0
T1	194803	194742	0	0
T2	117406	117397	0	0
T3	966652	966576	0	0
T4	290427	290364	0	0
T5	101845	101837	0	0
T6	1369	1277	0	0
T7	34451	34359	0	0
T8	148284	148206	0	0
T9	142344	142273	0	0
T10	1773	1696	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488260216	488125270	0	0
T1	194803	194742	0	0
T2	117406	117397	0	0
T3	966652	966576	0	0
T4	290427	290364	0	0
T5	101845	101837	0	0
T6	1369	1277	0	0
T7	34451	34359	0	0
T8	148284	148206	0	0
T9	142344	142273	0	0
T10	1773	1696	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	488260216	3076277	0	0
DepthKnown_A	488260216	488125270	0	0
RvalidKnown_A	488260216	488125270	0	0
WreadyKnown_A	488260216	488125270	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488260216	3076277	0	0
T1	194803	12345	0	0
T2	117406	5824	0	0
T3	966652	6656	0	0
T4	290427	832	0	0
T5	101845	24625	0	0
T6	1369	0	0	0
T7	34451	2524	0	0
T8	148284	2496	0	0
T9	142344	832	0	0
T10	1773	0	0	0
T11	0	832	0	0
T12	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488260216	488125270	0	0
T1	194803	194742	0	0
T2	117406	117397	0	0
T3	966652	966576	0	0
T4	290427	290364	0	0
T5	101845	101837	0	0
T6	1369	1277	0	0
T7	34451	34359	0	0
T8	148284	148206	0	0
T9	142344	142273	0	0
T10	1773	1696	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488260216	488125270	0	0
T1	194803	194742	0	0
T2	117406	117397	0	0
T3	966652	966576	0	0
T4	290427	290364	0	0
T5	101845	101837	0	0
T6	1369	1277	0	0
T7	34451	34359	0	0
T8	148284	148206	0	0
T9	142344	142273	0	0
T10	1773	1696	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488260216	488125270	0	0
T1	194803	194742	0	0
T2	117406	117397	0	0
T3	966652	966576	0	0
T4	290427	290364	0	0
T5	101845	101837	0	0
T6	1369	1277	0	0
T7	34451	34359	0	0
T8	148284	148206	0	0
T9	142344	142273	0	0
T10	1773	1696	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	488260216	187209	0	0
DepthKnown_A	488260216	488125270	0	0
RvalidKnown_A	488260216	488125270	0	0
WreadyKnown_A	488260216	488125270	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488260216	187209	0	0
T1	194803	611	0	0
T2	117406	1032	0	0
T3	966652	702	0	0
T4	290427	0	0	0
T5	101845	519	0	0
T6	1369	0	0	0
T7	34451	0	0	0
T8	148284	344	0	0
T9	142344	0	0	0
T10	1773	1	0	0
T13	0	1536	0	0
T25	0	62	0	0
T27	0	807	0	0
T38	0	704	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488260216	488125270	0	0
T1	194803	194742	0	0
T2	117406	117397	0	0
T3	966652	966576	0	0
T4	290427	290364	0	0
T5	101845	101837	0	0
T6	1369	1277	0	0
T7	34451	34359	0	0
T8	148284	148206	0	0
T9	142344	142273	0	0
T10	1773	1696	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488260216	488125270	0	0
T1	194803	194742	0	0
T2	117406	117397	0	0
T3	966652	966576	0	0
T4	290427	290364	0	0
T5	101845	101837	0	0
T6	1369	1277	0	0
T7	34451	34359	0	0
T8	148284	148206	0	0
T9	142344	142273	0	0
T10	1773	1696	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488260216	488125270	0	0
T1	194803	194742	0	0
T2	117406	117397	0	0
T3	966652	966576	0	0
T4	290427	290364	0	0
T5	101845	101837	0	0
T6	1369	1277	0	0
T7	34451	34359	0	0
T8	148284	148206	0	0
T9	142344	142273	0	0
T10	1773	1696	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	488260216	398090	0	0
DepthKnown_A	488260216	488125270	0	0
RvalidKnown_A	488260216	488125270	0	0
WreadyKnown_A	488260216	488125270	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488260216	398090	0	0
T1	194803	2871	0	0
T2	117406	1031	0	0
T3	966652	702	0	0
T4	290427	0	0	0
T5	101845	1589	0	0
T6	1369	0	0	0
T7	34451	0	0	0
T8	148284	344	0	0
T9	142344	0	0	0
T10	1773	1	0	0
T13	0	1533	0	0
T25	0	277	0	0
T27	0	2497	0	0
T38	0	704	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488260216	488125270	0	0
T1	194803	194742	0	0
T2	117406	117397	0	0
T3	966652	966576	0	0
T4	290427	290364	0	0
T5	101845	101837	0	0
T6	1369	1277	0	0
T7	34451	34359	0	0
T8	148284	148206	0	0
T9	142344	142273	0	0
T10	1773	1696	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488260216	488125270	0	0
T1	194803	194742	0	0
T2	117406	117397	0	0
T3	966652	966576	0	0
T4	290427	290364	0	0
T5	101845	101837	0	0
T6	1369	1277	0	0
T7	34451	34359	0	0
T8	148284	148206	0	0
T9	142344	142273	0	0
T10	1773	1696	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488260216	488125270	0	0
T1	194803	194742	0	0
T2	117406	117397	0	0
T3	966652	966576	0	0
T4	290427	290364	0	0
T5	101845	101837	0	0
T6	1369	1277	0	0
T7	34451	34359	0	0
T8	148284	148206	0	0
T9	142344	142273	0	0
T10	1773	1696	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	488260216	6201588	0	0
DepthKnown_A	488260216	488125270	0	0
RvalidKnown_A	488260216	488125270	0	0
WreadyKnown_A	488260216	488125270	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488260216	6201588	0	0
T1	194803	4883	0	0
T2	117406	23853	0	0
T3	966652	2156	0	0
T4	290427	480	0	0
T5	101845	2984	0	0
T6	1369	4	0	0
T7	34451	1251	0	0
T8	148284	4023	0	0
T9	142344	5209	0	0
T10	1773	90	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488260216	488125270	0	0
T1	194803	194742	0	0
T2	117406	117397	0	0
T3	966652	966576	0	0
T4	290427	290364	0	0
T5	101845	101837	0	0
T6	1369	1277	0	0
T7	34451	34359	0	0
T8	148284	148206	0	0
T9	142344	142273	0	0
T10	1773	1696	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488260216	488125270	0	0
T1	194803	194742	0	0
T2	117406	117397	0	0
T3	966652	966576	0	0
T4	290427	290364	0	0
T5	101845	101837	0	0
T6	1369	1277	0	0
T7	34451	34359	0	0
T8	148284	148206	0	0
T9	142344	142273	0	0
T10	1773	1696	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488260216	488125270	0	0
T1	194803	194742	0	0
T2	117406	117397	0	0
T3	966652	966576	0	0
T4	290427	290364	0	0
T5	101845	101837	0	0
T6	1369	1277	0	0
T7	34451	34359	0	0
T8	148284	148206	0	0
T9	142344	142273	0	0
T10	1773	1696	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	488260216	11978604	0	0
DepthKnown_A	488260216	488125270	0	0
RvalidKnown_A	488260216	488125270	0	0
WreadyKnown_A	488260216	488125270	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488260216	11978604	0	0
T1	194803	19671	0	0
T2	117406	23659	0	0
T3	966652	2148	0	0
T4	290427	1869	0	0
T5	101845	8781	0	0
T6	1369	8	0	0
T7	34451	4050	0	0
T8	148284	3988	0	0
T9	142344	5209	0	0
T10	1773	90	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488260216	488125270	0	0
T1	194803	194742	0	0
T2	117406	117397	0	0
T3	966652	966576	0	0
T4	290427	290364	0	0
T5	101845	101837	0	0
T6	1369	1277	0	0
T7	34451	34359	0	0
T8	148284	148206	0	0
T9	142344	142273	0	0
T10	1773	1696	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488260216	488125270	0	0
T1	194803	194742	0	0
T2	117406	117397	0	0
T3	966652	966576	0	0
T4	290427	290364	0	0
T5	101845	101837	0	0
T6	1369	1277	0	0
T7	34451	34359	0	0
T8	148284	148206	0	0
T9	142344	142273	0	0
T10	1773	1696	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488260216	488125270	0	0
T1	194803	194742	0	0
T2	117406	117397	0	0
T3	966652	966576	0	0
T4	290427	290364	0	0
T5	101845	101837	0	0
T6	1369	1277	0	0
T7	34451	34359	0	0
T8	148284	148206	0	0
T9	142344	142273	0	0
T10	1773	1696	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0