Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Unreachable
1	1	Covered	T1,T2,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	786278041	634553345	0	0
CheckNGreaterZero_A	2865	2865	0	0
GntImpliesReady_A	786278041	3734175	0	0
GntImpliesValid_A	786278041	3734175	0	0
GrantKnown_A	786278041	634553345	0	0
IdxKnown_A	786278041	634553345	0	0
IndexIsCorrect_A	786278041	3734175	0	0
LockArbDecision_A	786278041	0	0	0
NoReadyValidNoGrant_A	786278041	0	0	0
ReadyAndValidImplyGrant_A	786278041	3734175	0	0
ReqAndReadyImplyGrant_A	786278041	3734175	0	0
ReqImpliesValid_A	786278041	3734175	0	0
ReqStaysHighUntilGranted0_M	786278041	0	0	0
RoundRobin_A	786278041	6	0	955
ValidKnown_A	786278041	634553345	0	0
gen_data_port_assertion.DataFlow_A	786278041	3734175	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	786278041	634553345	0	0
T1	561085	375101	0	0
T2	863118	483735	0	0
T3	1585672	1273467	0	0
T4	405103	347702	0	0
T5	1932969	1011971	0	0
T6	1369	1277	0	0
T7	42891	38579	0	0
T8	863076	502931	0	0
T9	682104	412153	0	0
T10	5517	3568	0	0
T11	51354	25296	0	0
T12	0	8732	0	0
T31	0	216	0	0
T32	0	288	0	0
T33	0	88368	0	0
T35	0	62240	0	0
T36	0	864	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2865	2865	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	786278041	3734175	0	0
T1	561085	9408	0	0
T2	863118	17570	0	0
T3	1585672	15106	0	0
T4	405103	832	0	0
T5	1932969	16980	0	0
T6	1369	0	0	0
T7	42891	832	0	0
T8	863076	5568	0	0
T9	682104	832	0	0
T10	5517	89	0	0
T11	51354	832	0	0
T13	0	11017	0	0
T14	0	2232	0	0
T15	0	3693	0	0
T25	0	265	0	0
T27	0	8940	0	0
T38	0	4636	0	0
T40	0	8980	0	0
T41	0	2067	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	786278041	3734175	0	0
T1	561085	9408	0	0
T2	863118	17570	0	0
T3	1585672	15106	0	0
T4	405103	832	0	0
T5	1932969	16980	0	0
T6	1369	0	0	0
T7	42891	832	0	0
T8	863076	5568	0	0
T9	682104	832	0	0
T10	5517	89	0	0
T11	51354	832	0	0
T13	0	11017	0	0
T14	0	2232	0	0
T15	0	3693	0	0
T25	0	265	0	0
T27	0	8940	0	0
T38	0	4636	0	0
T40	0	8980	0	0
T41	0	2067	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	786278041	634553345	0	0
T1	561085	375101	0	0
T2	863118	483735	0	0
T3	1585672	1273467	0	0
T4	405103	347702	0	0
T5	1932969	1011971	0	0
T6	1369	1277	0	0
T7	42891	38579	0	0
T8	863076	502931	0	0
T9	682104	412153	0	0
T10	5517	3568	0	0
T11	51354	25296	0	0
T12	0	8732	0	0
T31	0	216	0	0
T32	0	288	0	0
T33	0	88368	0	0
T35	0	62240	0	0
T36	0	864	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	786278041	634553345	0	0
T1	561085	375101	0	0
T2	863118	483735	0	0
T3	1585672	1273467	0	0
T4	405103	347702	0	0
T5	1932969	1011971	0	0
T6	1369	1277	0	0
T7	42891	38579	0	0
T8	863076	502931	0	0
T9	682104	412153	0	0
T10	5517	3568	0	0
T11	51354	25296	0	0
T12	0	8732	0	0
T31	0	216	0	0
T32	0	288	0	0
T33	0	88368	0	0
T35	0	62240	0	0
T36	0	864	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	786278041	3734175	0	0
T1	561085	9408	0	0
T2	863118	17570	0	0
T3	1585672	15106	0	0
T4	405103	832	0	0
T5	1932969	16980	0	0
T6	1369	0	0	0
T7	42891	832	0	0
T8	863076	5568	0	0
T9	682104	832	0	0
T10	5517	89	0	0
T11	51354	832	0	0
T13	0	11017	0	0
T14	0	2232	0	0
T15	0	3693	0	0
T25	0	265	0	0
T27	0	8940	0	0
T38	0	4636	0	0
T40	0	8980	0	0
T41	0	2067	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	786278041	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	786278041	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	786278041	3734175	0	0
T1	561085	9408	0	0
T2	863118	17570	0	0
T3	1585672	15106	0	0
T4	405103	832	0	0
T5	1932969	16980	0	0
T6	1369	0	0	0
T7	42891	832	0	0
T8	863076	5568	0	0
T9	682104	832	0	0
T10	5517	89	0	0
T11	51354	832	0	0
T13	0	11017	0	0
T14	0	2232	0	0
T15	0	3693	0	0
T25	0	265	0	0
T27	0	8940	0	0
T38	0	4636	0	0
T40	0	8980	0	0
T41	0	2067	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	786278041	3734175	0	0
T1	561085	9408	0	0
T2	863118	17570	0	0
T3	1585672	15106	0	0
T4	405103	832	0	0
T5	1932969	16980	0	0
T6	1369	0	0	0
T7	42891	832	0	0
T8	863076	5568	0	0
T9	682104	832	0	0
T10	5517	89	0	0
T11	51354	832	0	0
T13	0	11017	0	0
T14	0	2232	0	0
T15	0	3693	0	0
T25	0	265	0	0
T27	0	8940	0	0
T38	0	4636	0	0
T40	0	8980	0	0
T41	0	2067	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	786278041	3734175	0	0
T1	561085	9408	0	0
T2	863118	17570	0	0
T3	1585672	15106	0	0
T4	405103	832	0	0
T5	1932969	16980	0	0
T6	1369	0	0	0
T7	42891	832	0	0
T8	863076	5568	0	0
T9	682104	832	0	0
T10	5517	89	0	0
T11	51354	832	0	0
T13	0	11017	0	0
T14	0	2232	0	0
T15	0	3693	0	0
T25	0	265	0	0
T27	0	8940	0	0
T38	0	4636	0	0
T40	0	8980	0	0
T41	0	2067	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	786278041	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	786278041	6	0	955
T20	143482	1	0	1
T21	562766	0	0	1
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	322206	0	0	1
T53	228552	0	0	1
T54	1844	0	0	1
T55	23636	0	0	1
T56	8698	0	0	1
T57	1076	0	0	1
T58	116019	0	0	1
T59	3248	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	786278041	634553345	0	0
T1	561085	375101	0	0
T2	863118	483735	0	0
T3	1585672	1273467	0	0
T4	405103	347702	0	0
T5	1932969	1011971	0	0
T6	1369	1277	0	0
T7	42891	38579	0	0
T8	863076	502931	0	0
T9	682104	412153	0	0
T10	5517	3568	0	0
T11	51354	25296	0	0
T12	0	8732	0	0
T31	0	216	0	0
T32	0	288	0	0
T33	0	88368	0	0
T35	0	62240	0	0
T36	0	864	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	786278041	3734175	0	0
T1	561085	9408	0	0
T2	863118	17570	0	0
T3	1585672	15106	0	0
T4	405103	832	0	0
T5	1932969	16980	0	0
T6	1369	0	0	0
T7	42891	832	0	0
T8	863076	5568	0	0
T9	682104	832	0	0
T10	5517	89	0	0
T11	51354	832	0	0
T13	0	11017	0	0
T14	0	2232	0	0
T15	0	3693	0	0
T25	0	265	0	0
T27	0	8940	0	0
T38	0	4636	0	0
T40	0	8980	0	0
T41	0	2067	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Unreachable
1	1	Covered	T1,T2,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	150274106	28785900	0	0
CheckNGreaterZero_A	955	955	0	0
GntImpliesReady_A	150274106	637661	0	0
GntImpliesValid_A	150274106	637661	0	0
GrantKnown_A	150274106	28785900	0	0
IdxKnown_A	150274106	28785900	0	0
IndexIsCorrect_A	150274106	637661	0	0
LockArbDecision_A	150274106	0	0	0
NoReadyValidNoGrant_A	150274106	0	0	0
ReadyAndValidImplyGrant_A	150274106	637661	0	0
ReqAndReadyImplyGrant_A	150274106	637661	0	0
ReqImpliesValid_A	150274106	637661	0	0
ReqStaysHighUntilGranted0_M	150274106	0	0	0
RoundRobin_A	150274106	0	0	0
ValidKnown_A	150274106	28785900	0	0
gen_data_port_assertion.DataFlow_A	150274106	637661	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150274106	28785900	0	0
T1	183141	74640	0	0
T2	372856	157672	0	0
T3	309510	0	0	0
T4	57338	0	0	0
T5	915562	14624	0	0
T7	4220	0	0	0
T8	357396	155152	0	0
T9	269880	0	0	0
T10	1872	1872	0	0
T11	25677	0	0	0
T31	0	216	0	0
T32	0	288	0	0
T33	0	88368	0	0
T35	0	62240	0	0
T36	0	864	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	955	955	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150274106	637661	0	0
T1	183141	2037	0	0
T2	372856	6013	0	0
T3	309510	0	0	0
T4	57338	0	0	0
T5	915562	355	0	0
T7	4220	0	0	0
T8	357396	1880	0	0
T9	269880	0	0	0
T10	1872	46	0	0
T11	25677	0	0	0
T13	0	6919	0	0
T14	0	2232	0	0
T25	0	265	0	0
T27	0	1367	0	0
T38	0	4636	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150274106	637661	0	0
T1	183141	2037	0	0
T2	372856	6013	0	0
T3	309510	0	0	0
T4	57338	0	0	0
T5	915562	355	0	0
T7	4220	0	0	0
T8	357396	1880	0	0
T9	269880	0	0	0
T10	1872	46	0	0
T11	25677	0	0	0
T13	0	6919	0	0
T14	0	2232	0	0
T25	0	265	0	0
T27	0	1367	0	0
T38	0	4636	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150274106	28785900	0	0
T1	183141	74640	0	0
T2	372856	157672	0	0
T3	309510	0	0	0
T4	57338	0	0	0
T5	915562	14624	0	0
T7	4220	0	0	0
T8	357396	155152	0	0
T9	269880	0	0	0
T10	1872	1872	0	0
T11	25677	0	0	0
T31	0	216	0	0
T32	0	288	0	0
T33	0	88368	0	0
T35	0	62240	0	0
T36	0	864	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150274106	28785900	0	0
T1	183141	74640	0	0
T2	372856	157672	0	0
T3	309510	0	0	0
T4	57338	0	0	0
T5	915562	14624	0	0
T7	4220	0	0	0
T8	357396	155152	0	0
T9	269880	0	0	0
T10	1872	1872	0	0
T11	25677	0	0	0
T31	0	216	0	0
T32	0	288	0	0
T33	0	88368	0	0
T35	0	62240	0	0
T36	0	864	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150274106	637661	0	0
T1	183141	2037	0	0
T2	372856	6013	0	0
T3	309510	0	0	0
T4	57338	0	0	0
T5	915562	355	0	0
T7	4220	0	0	0
T8	357396	1880	0	0
T9	269880	0	0	0
T10	1872	46	0	0
T11	25677	0	0	0
T13	0	6919	0	0
T14	0	2232	0	0
T25	0	265	0	0
T27	0	1367	0	0
T38	0	4636	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150274106	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150274106	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150274106	637661	0	0
T1	183141	2037	0	0
T2	372856	6013	0	0
T3	309510	0	0	0
T4	57338	0	0	0
T5	915562	355	0	0
T7	4220	0	0	0
T8	357396	1880	0	0
T9	269880	0	0	0
T10	1872	46	0	0
T11	25677	0	0	0
T13	0	6919	0	0
T14	0	2232	0	0
T25	0	265	0	0
T27	0	1367	0	0
T38	0	4636	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150274106	637661	0	0
T1	183141	2037	0	0
T2	372856	6013	0	0
T3	309510	0	0	0
T4	57338	0	0	0
T5	915562	355	0	0
T7	4220	0	0	0
T8	357396	1880	0	0
T9	269880	0	0	0
T10	1872	46	0	0
T11	25677	0	0	0
T13	0	6919	0	0
T14	0	2232	0	0
T25	0	265	0	0
T27	0	1367	0	0
T38	0	4636	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150274106	637661	0	0
T1	183141	2037	0	0
T2	372856	6013	0	0
T3	309510	0	0	0
T4	57338	0	0	0
T5	915562	355	0	0
T7	4220	0	0	0
T8	357396	1880	0	0
T9	269880	0	0	0
T10	1872	46	0	0
T11	25677	0	0	0
T13	0	6919	0	0
T14	0	2232	0	0
T25	0	265	0	0
T27	0	1367	0	0
T38	0	4636	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	150274106	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150274106	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150274106	28785900	0	0
T1	183141	74640	0	0
T2	372856	157672	0	0
T3	309510	0	0	0
T4	57338	0	0	0
T5	915562	14624	0	0
T7	4220	0	0	0
T8	357396	155152	0	0
T9	269880	0	0	0
T10	1872	1872	0	0
T11	25677	0	0	0
T31	0	216	0	0
T32	0	288	0	0
T33	0	88368	0	0
T35	0	62240	0	0
T36	0	864	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150274106	637661	0	0
T1	183141	2037	0	0
T2	372856	6013	0	0
T3	309510	0	0	0
T4	57338	0	0	0
T5	915562	355	0	0
T7	4220	0	0	0
T8	357396	1880	0	0
T9	269880	0	0	0
T10	1872	46	0	0
T11	25677	0	0	0
T13	0	6919	0	0
T14	0	2232	0	0
T25	0	265	0	0
T27	0	1367	0	0
T38	0	4636	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	150274106	120125772	0	0
CheckNGreaterZero_A	955	955	0	0
GntImpliesReady_A	150274106	840014	0	0
GntImpliesValid_A	150274106	840014	0	0
GrantKnown_A	150274106	120125772	0	0
IdxKnown_A	150274106	120125772	0	0
IndexIsCorrect_A	150274106	840014	0	0
LockArbDecision_A	150274106	0	0	0
NoReadyValidNoGrant_A	150274106	0	0	0
ReadyAndValidImplyGrant_A	150274106	840014	0	0
ReqAndReadyImplyGrant_A	150274106	840014	0	0
ReqImpliesValid_A	150274106	840014	0	0
ReqStaysHighUntilGranted0_M	150274106	0	0	0
RoundRobin_A	150274106	0	0	0
ValidKnown_A	150274106	120125772	0	0
gen_data_port_assertion.DataFlow_A	150274106	840014	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150274106	120125772	0	0
T1	183141	105719	0	0
T2	372856	208666	0	0
T3	309510	306891	0	0
T4	57338	57338	0	0
T5	915562	895510	0	0
T7	4220	4220	0	0
T8	357396	199573	0	0
T9	269880	269880	0	0
T10	1872	0	0	0
T11	25677	25296	0	0
T12	0	8732	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	955	955	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150274106	840014	0	0
T1	183141	2915	0	0
T2	372856	2622	0	0
T3	309510	7727	0	0
T4	57338	0	0	0
T5	915562	5173	0	0
T7	4220	0	0	0
T8	357396	181	0	0
T9	269880	0	0	0
T10	1872	0	0	0
T11	25677	0	0	0
T13	0	4098	0	0
T15	0	3693	0	0
T27	0	7573	0	0
T40	0	8980	0	0
T41	0	2067	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150274106	840014	0	0
T1	183141	2915	0	0
T2	372856	2622	0	0
T3	309510	7727	0	0
T4	57338	0	0	0
T5	915562	5173	0	0
T7	4220	0	0	0
T8	357396	181	0	0
T9	269880	0	0	0
T10	1872	0	0	0
T11	25677	0	0	0
T13	0	4098	0	0
T15	0	3693	0	0
T27	0	7573	0	0
T40	0	8980	0	0
T41	0	2067	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150274106	120125772	0	0
T1	183141	105719	0	0
T2	372856	208666	0	0
T3	309510	306891	0	0
T4	57338	57338	0	0
T5	915562	895510	0	0
T7	4220	4220	0	0
T8	357396	199573	0	0
T9	269880	269880	0	0
T10	1872	0	0	0
T11	25677	25296	0	0
T12	0	8732	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150274106	120125772	0	0
T1	183141	105719	0	0
T2	372856	208666	0	0
T3	309510	306891	0	0
T4	57338	57338	0	0
T5	915562	895510	0	0
T7	4220	4220	0	0
T8	357396	199573	0	0
T9	269880	269880	0	0
T10	1872	0	0	0
T11	25677	25296	0	0
T12	0	8732	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150274106	840014	0	0
T1	183141	2915	0	0
T2	372856	2622	0	0
T3	309510	7727	0	0
T4	57338	0	0	0
T5	915562	5173	0	0
T7	4220	0	0	0
T8	357396	181	0	0
T9	269880	0	0	0
T10	1872	0	0	0
T11	25677	0	0	0
T13	0	4098	0	0
T15	0	3693	0	0
T27	0	7573	0	0
T40	0	8980	0	0
T41	0	2067	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150274106	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150274106	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150274106	840014	0	0
T1	183141	2915	0	0
T2	372856	2622	0	0
T3	309510	7727	0	0
T4	57338	0	0	0
T5	915562	5173	0	0
T7	4220	0	0	0
T8	357396	181	0	0
T9	269880	0	0	0
T10	1872	0	0	0
T11	25677	0	0	0
T13	0	4098	0	0
T15	0	3693	0	0
T27	0	7573	0	0
T40	0	8980	0	0
T41	0	2067	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150274106	840014	0	0
T1	183141	2915	0	0
T2	372856	2622	0	0
T3	309510	7727	0	0
T4	57338	0	0	0
T5	915562	5173	0	0
T7	4220	0	0	0
T8	357396	181	0	0
T9	269880	0	0	0
T10	1872	0	0	0
T11	25677	0	0	0
T13	0	4098	0	0
T15	0	3693	0	0
T27	0	7573	0	0
T40	0	8980	0	0
T41	0	2067	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150274106	840014	0	0
T1	183141	2915	0	0
T2	372856	2622	0	0
T3	309510	7727	0	0
T4	57338	0	0	0
T5	915562	5173	0	0
T7	4220	0	0	0
T8	357396	181	0	0
T9	269880	0	0	0
T10	1872	0	0	0
T11	25677	0	0	0
T13	0	4098	0	0
T15	0	3693	0	0
T27	0	7573	0	0
T40	0	8980	0	0
T41	0	2067	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	150274106	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150274106	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150274106	120125772	0	0
T1	183141	105719	0	0
T2	372856	208666	0	0
T3	309510	306891	0	0
T4	57338	57338	0	0
T5	915562	895510	0	0
T7	4220	4220	0	0
T8	357396	199573	0	0
T9	269880	269880	0	0
T10	1872	0	0	0
T11	25677	25296	0	0
T12	0	8732	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150274106	840014	0	0
T1	183141	2915	0	0
T2	372856	2622	0	0
T3	309510	7727	0	0
T4	57338	0	0	0
T5	915562	5173	0	0
T7	4220	0	0	0
T8	357396	181	0	0
T9	269880	0	0	0
T10	1872	0	0	0
T11	25677	0	0	0
T13	0	4098	0	0
T15	0	3693	0	0
T27	0	7573	0	0
T40	0	8980	0	0
T41	0	2067	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	485729829	485641673	0	0
CheckNGreaterZero_A	955	955	0	0
GntImpliesReady_A	485729829	2256500	0	0
GntImpliesValid_A	485729829	2256500	0	0
GrantKnown_A	485729829	485641673	0	0
IdxKnown_A	485729829	485641673	0	0
IndexIsCorrect_A	485729829	2256500	0	0
LockArbDecision_A	485729829	0	0	0
NoReadyValidNoGrant_A	485729829	0	0	0
ReadyAndValidImplyGrant_A	485729829	2256500	0	0
ReqAndReadyImplyGrant_A	485729829	2256500	0	0
ReqImpliesValid_A	485729829	2256500	0	0
ReqStaysHighUntilGranted0_M	485729829	0	0	0
RoundRobin_A	485729829	6	0	955
ValidKnown_A	485729829	485641673	0	0
gen_data_port_assertion.DataFlow_A	485729829	2256500	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485729829	485641673	0	0
T1	194803	194742	0	0
T2	117406	117397	0	0
T3	966652	966576	0	0
T4	290427	290364	0	0
T5	101845	101837	0	0
T6	1369	1277	0	0
T7	34451	34359	0	0
T8	148284	148206	0	0
T9	142344	142273	0	0
T10	1773	1696	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	955	955	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485729829	2256500	0	0
T1	194803	4456	0	0
T2	117406	8935	0	0
T3	966652	7379	0	0
T4	290427	832	0	0
T5	101845	11452	0	0
T6	1369	0	0	0
T7	34451	832	0	0
T8	148284	3507	0	0
T9	142344	832	0	0
T10	1773	43	0	0
T11	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485729829	2256500	0	0
T1	194803	4456	0	0
T2	117406	8935	0	0
T3	966652	7379	0	0
T4	290427	832	0	0
T5	101845	11452	0	0
T6	1369	0	0	0
T7	34451	832	0	0
T8	148284	3507	0	0
T9	142344	832	0	0
T10	1773	43	0	0
T11	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485729829	485641673	0	0
T1	194803	194742	0	0
T2	117406	117397	0	0
T3	966652	966576	0	0
T4	290427	290364	0	0
T5	101845	101837	0	0
T6	1369	1277	0	0
T7	34451	34359	0	0
T8	148284	148206	0	0
T9	142344	142273	0	0
T10	1773	1696	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485729829	485641673	0	0
T1	194803	194742	0	0
T2	117406	117397	0	0
T3	966652	966576	0	0
T4	290427	290364	0	0
T5	101845	101837	0	0
T6	1369	1277	0	0
T7	34451	34359	0	0
T8	148284	148206	0	0
T9	142344	142273	0	0
T10	1773	1696	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485729829	2256500	0	0
T1	194803	4456	0	0
T2	117406	8935	0	0
T3	966652	7379	0	0
T4	290427	832	0	0
T5	101845	11452	0	0
T6	1369	0	0	0
T7	34451	832	0	0
T8	148284	3507	0	0
T9	142344	832	0	0
T10	1773	43	0	0
T11	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485729829	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485729829	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485729829	2256500	0	0
T1	194803	4456	0	0
T2	117406	8935	0	0
T3	966652	7379	0	0
T4	290427	832	0	0
T5	101845	11452	0	0
T6	1369	0	0	0
T7	34451	832	0	0
T8	148284	3507	0	0
T9	142344	832	0	0
T10	1773	43	0	0
T11	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485729829	2256500	0	0
T1	194803	4456	0	0
T2	117406	8935	0	0
T3	966652	7379	0	0
T4	290427	832	0	0
T5	101845	11452	0	0
T6	1369	0	0	0
T7	34451	832	0	0
T8	148284	3507	0	0
T9	142344	832	0	0
T10	1773	43	0	0
T11	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485729829	2256500	0	0
T1	194803	4456	0	0
T2	117406	8935	0	0
T3	966652	7379	0	0
T4	290427	832	0	0
T5	101845	11452	0	0
T6	1369	0	0	0
T7	34451	832	0	0
T8	148284	3507	0	0
T9	142344	832	0	0
T10	1773	43	0	0
T11	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	485729829	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485729829	6	0	955
T20	143482	1	0	1
T21	562766	0	0	1
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	322206	0	0	1
T53	228552	0	0	1
T54	1844	0	0	1
T55	23636	0	0	1
T56	8698	0	0	1
T57	1076	0	0	1
T58	116019	0	0	1
T59	3248	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485729829	485641673	0	0
T1	194803	194742	0	0
T2	117406	117397	0	0
T3	966652	966576	0	0
T4	290427	290364	0	0
T5	101845	101837	0	0
T6	1369	1277	0	0
T7	34451	34359	0	0
T8	148284	148206	0	0
T9	142344	142273	0	0
T10	1773	1696	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485729829	2256500	0	0
T1	194803	4456	0	0
T2	117406	8935	0	0
T3	966652	7379	0	0
T4	290427	832	0	0
T5	101845	11452	0	0
T6	1369	0	0	0
T7	34451	832	0	0
T8	148284	3507	0	0
T9	142344	832	0	0
T10	1773	43	0	0
T11	0	832	0	0