Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
3509 |
0 |
0 |
T62 |
2760 |
2 |
0 |
0 |
T63 |
100551 |
4 |
0 |
0 |
T64 |
19346 |
6 |
0 |
0 |
T94 |
3944 |
179 |
0 |
0 |
T95 |
15444 |
269 |
0 |
0 |
T96 |
54929 |
2 |
0 |
0 |
T97 |
6856 |
97 |
0 |
0 |
T106 |
29103 |
8 |
0 |
0 |
T107 |
29579 |
2 |
0 |
0 |
T108 |
63101 |
2 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
2779 |
0 |
0 |
T63 |
100551 |
108 |
0 |
0 |
T108 |
63101 |
38 |
0 |
0 |
T114 |
7183 |
2 |
0 |
0 |
T115 |
3570 |
8 |
0 |
0 |
T117 |
180538 |
442 |
0 |
0 |
T120 |
11786 |
16 |
0 |
0 |
T146 |
3909 |
3 |
0 |
0 |
T147 |
7726 |
51 |
0 |
0 |
T148 |
13224 |
41 |
0 |
0 |
T149 |
31303 |
50 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
2804 |
0 |
0 |
T63 |
100551 |
131 |
0 |
0 |
T108 |
63101 |
28 |
0 |
0 |
T114 |
7183 |
3 |
0 |
0 |
T117 |
180538 |
443 |
0 |
0 |
T119 |
4181 |
4 |
0 |
0 |
T120 |
11786 |
16 |
0 |
0 |
T146 |
3909 |
5 |
0 |
0 |
T147 |
7726 |
9 |
0 |
0 |
T148 |
13224 |
87 |
0 |
0 |
T149 |
31303 |
31 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
3138 |
0 |
0 |
T63 |
100551 |
209 |
0 |
0 |
T108 |
63101 |
83 |
0 |
0 |
T114 |
7183 |
20 |
0 |
0 |
T115 |
3570 |
1 |
0 |
0 |
T117 |
180538 |
460 |
0 |
0 |
T120 |
11786 |
24 |
0 |
0 |
T146 |
3909 |
2 |
0 |
0 |
T147 |
7726 |
10 |
0 |
0 |
T148 |
13224 |
18 |
0 |
0 |
T149 |
31303 |
67 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
9493 |
0 |
0 |
T63 |
100551 |
1668 |
0 |
0 |
T108 |
63101 |
705 |
0 |
0 |
T114 |
7183 |
106 |
0 |
0 |
T115 |
3570 |
22 |
0 |
0 |
T117 |
180538 |
508 |
0 |
0 |
T119 |
4181 |
76 |
0 |
0 |
T120 |
11786 |
113 |
0 |
0 |
T146 |
3909 |
5 |
0 |
0 |
T147 |
7726 |
29 |
0 |
0 |
T148 |
13224 |
35 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
10440 |
0 |
0 |
T63 |
100551 |
1974 |
0 |
0 |
T108 |
63101 |
867 |
0 |
0 |
T114 |
7183 |
8 |
0 |
0 |
T115 |
3570 |
68 |
0 |
0 |
T117 |
180538 |
464 |
0 |
0 |
T119 |
4181 |
52 |
0 |
0 |
T120 |
11786 |
102 |
0 |
0 |
T147 |
7726 |
13 |
0 |
0 |
T148 |
13224 |
49 |
0 |
0 |
T149 |
31303 |
573 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
9147 |
0 |
0 |
T63 |
100551 |
1436 |
0 |
0 |
T108 |
63101 |
702 |
0 |
0 |
T114 |
7183 |
146 |
0 |
0 |
T115 |
3570 |
56 |
0 |
0 |
T117 |
180538 |
444 |
0 |
0 |
T119 |
4181 |
3 |
0 |
0 |
T120 |
11786 |
331 |
0 |
0 |
T146 |
3909 |
1 |
0 |
0 |
T147 |
7726 |
7 |
0 |
0 |
T149 |
31303 |
248 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
9997 |
0 |
0 |
T63 |
100551 |
1717 |
0 |
0 |
T108 |
63101 |
758 |
0 |
0 |
T114 |
7183 |
96 |
0 |
0 |
T115 |
3570 |
54 |
0 |
0 |
T117 |
180538 |
454 |
0 |
0 |
T119 |
4181 |
36 |
0 |
0 |
T120 |
11786 |
257 |
0 |
0 |
T146 |
3909 |
9 |
0 |
0 |
T147 |
7726 |
34 |
0 |
0 |
T148 |
13224 |
63 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
10182 |
0 |
0 |
T63 |
100551 |
1935 |
0 |
0 |
T108 |
63101 |
707 |
0 |
0 |
T114 |
7183 |
110 |
0 |
0 |
T115 |
3570 |
2 |
0 |
0 |
T117 |
180538 |
426 |
0 |
0 |
T120 |
11786 |
138 |
0 |
0 |
T146 |
3909 |
4 |
0 |
0 |
T147 |
7726 |
25 |
0 |
0 |
T148 |
13224 |
63 |
0 |
0 |
T149 |
31303 |
525 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
10465 |
0 |
0 |
T63 |
100551 |
2075 |
0 |
0 |
T108 |
63101 |
686 |
0 |
0 |
T114 |
7183 |
214 |
0 |
0 |
T117 |
180538 |
490 |
0 |
0 |
T119 |
4181 |
41 |
0 |
0 |
T120 |
11786 |
385 |
0 |
0 |
T146 |
3909 |
5 |
0 |
0 |
T147 |
7726 |
3 |
0 |
0 |
T148 |
13224 |
15 |
0 |
0 |
T149 |
31303 |
665 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
10141 |
0 |
0 |
T63 |
100551 |
1707 |
0 |
0 |
T108 |
63101 |
627 |
0 |
0 |
T114 |
7183 |
116 |
0 |
0 |
T115 |
3570 |
2 |
0 |
0 |
T117 |
180538 |
401 |
0 |
0 |
T119 |
4181 |
55 |
0 |
0 |
T120 |
11786 |
112 |
0 |
0 |
T146 |
3909 |
165 |
0 |
0 |
T147 |
7726 |
38 |
0 |
0 |
T148 |
13224 |
36 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
9376 |
0 |
0 |
T63 |
100551 |
1257 |
0 |
0 |
T108 |
63101 |
508 |
0 |
0 |
T115 |
3570 |
69 |
0 |
0 |
T117 |
180538 |
436 |
0 |
0 |
T120 |
11786 |
17 |
0 |
0 |
T122 |
181051 |
457 |
0 |
0 |
T146 |
3909 |
146 |
0 |
0 |
T147 |
7726 |
19 |
0 |
0 |
T148 |
13224 |
58 |
0 |
0 |
T149 |
31303 |
608 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
5813 |
0 |
0 |
T63 |
100551 |
1006 |
0 |
0 |
T108 |
63101 |
196 |
0 |
0 |
T114 |
7183 |
8 |
0 |
0 |
T115 |
3570 |
25 |
0 |
0 |
T117 |
180538 |
402 |
0 |
0 |
T119 |
4181 |
9 |
0 |
0 |
T120 |
11786 |
102 |
0 |
0 |
T147 |
7726 |
23 |
0 |
0 |
T148 |
13224 |
38 |
0 |
0 |
T149 |
31303 |
240 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
5658 |
0 |
0 |
T63 |
100551 |
779 |
0 |
0 |
T108 |
63101 |
341 |
0 |
0 |
T114 |
7183 |
47 |
0 |
0 |
T115 |
3570 |
7 |
0 |
0 |
T117 |
180538 |
476 |
0 |
0 |
T119 |
4181 |
30 |
0 |
0 |
T120 |
11786 |
90 |
0 |
0 |
T146 |
3909 |
2 |
0 |
0 |
T147 |
7726 |
12 |
0 |
0 |
T148 |
13224 |
66 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
5396 |
0 |
0 |
T63 |
100551 |
697 |
0 |
0 |
T108 |
63101 |
332 |
0 |
0 |
T114 |
7183 |
5 |
0 |
0 |
T115 |
3570 |
6 |
0 |
0 |
T117 |
180538 |
404 |
0 |
0 |
T119 |
4181 |
11 |
0 |
0 |
T120 |
11786 |
115 |
0 |
0 |
T146 |
3909 |
1 |
0 |
0 |
T147 |
7726 |
30 |
0 |
0 |
T148 |
13224 |
61 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
5565 |
0 |
0 |
T63 |
100551 |
722 |
0 |
0 |
T108 |
63101 |
267 |
0 |
0 |
T114 |
7183 |
7 |
0 |
0 |
T115 |
3570 |
30 |
0 |
0 |
T117 |
180538 |
485 |
0 |
0 |
T120 |
11786 |
11 |
0 |
0 |
T146 |
3909 |
45 |
0 |
0 |
T147 |
7726 |
5 |
0 |
0 |
T148 |
13224 |
58 |
0 |
0 |
T149 |
31303 |
265 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
5282 |
0 |
0 |
T63 |
100551 |
793 |
0 |
0 |
T97 |
6856 |
6 |
0 |
0 |
T108 |
63101 |
190 |
0 |
0 |
T114 |
7183 |
8 |
0 |
0 |
T117 |
180538 |
467 |
0 |
0 |
T119 |
4181 |
14 |
0 |
0 |
T120 |
11786 |
116 |
0 |
0 |
T146 |
3909 |
73 |
0 |
0 |
T147 |
7726 |
23 |
0 |
0 |
T148 |
13224 |
32 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
5601 |
0 |
0 |
T63 |
100551 |
1028 |
0 |
0 |
T108 |
63101 |
328 |
0 |
0 |
T114 |
7183 |
93 |
0 |
0 |
T115 |
3570 |
24 |
0 |
0 |
T117 |
180538 |
369 |
0 |
0 |
T120 |
11786 |
116 |
0 |
0 |
T146 |
3909 |
9 |
0 |
0 |
T147 |
7726 |
14 |
0 |
0 |
T148 |
13224 |
19 |
0 |
0 |
T149 |
31303 |
122 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
5339 |
0 |
0 |
T63 |
100551 |
854 |
0 |
0 |
T108 |
63101 |
310 |
0 |
0 |
T114 |
7183 |
106 |
0 |
0 |
T115 |
3570 |
26 |
0 |
0 |
T117 |
180538 |
470 |
0 |
0 |
T119 |
4181 |
27 |
0 |
0 |
T120 |
11786 |
105 |
0 |
0 |
T146 |
3909 |
67 |
0 |
0 |
T147 |
7726 |
7 |
0 |
0 |
T148 |
13224 |
18 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
5539 |
0 |
0 |
T63 |
100551 |
622 |
0 |
0 |
T108 |
63101 |
316 |
0 |
0 |
T114 |
7183 |
59 |
0 |
0 |
T115 |
3570 |
48 |
0 |
0 |
T117 |
180538 |
445 |
0 |
0 |
T119 |
4181 |
1 |
0 |
0 |
T120 |
11786 |
53 |
0 |
0 |
T146 |
3909 |
31 |
0 |
0 |
T147 |
7726 |
8 |
0 |
0 |
T148 |
13224 |
31 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
5392 |
0 |
0 |
T63 |
100551 |
839 |
0 |
0 |
T108 |
63101 |
193 |
0 |
0 |
T114 |
7183 |
102 |
0 |
0 |
T117 |
180538 |
447 |
0 |
0 |
T120 |
11786 |
59 |
0 |
0 |
T122 |
181051 |
443 |
0 |
0 |
T146 |
3909 |
2 |
0 |
0 |
T147 |
7726 |
21 |
0 |
0 |
T148 |
13224 |
45 |
0 |
0 |
T149 |
31303 |
315 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
5412 |
0 |
0 |
T63 |
100551 |
688 |
0 |
0 |
T108 |
63101 |
192 |
0 |
0 |
T114 |
7183 |
56 |
0 |
0 |
T115 |
3570 |
7 |
0 |
0 |
T117 |
180538 |
427 |
0 |
0 |
T119 |
4181 |
24 |
0 |
0 |
T120 |
11786 |
115 |
0 |
0 |
T146 |
3909 |
9 |
0 |
0 |
T147 |
7726 |
31 |
0 |
0 |
T148 |
13224 |
34 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
5516 |
0 |
0 |
T63 |
100551 |
871 |
0 |
0 |
T108 |
63101 |
252 |
0 |
0 |
T114 |
7183 |
38 |
0 |
0 |
T115 |
3570 |
20 |
0 |
0 |
T117 |
180538 |
423 |
0 |
0 |
T120 |
11786 |
51 |
0 |
0 |
T146 |
3909 |
4 |
0 |
0 |
T147 |
7726 |
43 |
0 |
0 |
T148 |
13224 |
62 |
0 |
0 |
T149 |
31303 |
298 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
5739 |
0 |
0 |
T63 |
100551 |
709 |
0 |
0 |
T108 |
63101 |
316 |
0 |
0 |
T114 |
7183 |
46 |
0 |
0 |
T115 |
3570 |
27 |
0 |
0 |
T117 |
180538 |
482 |
0 |
0 |
T119 |
4181 |
6 |
0 |
0 |
T120 |
11786 |
47 |
0 |
0 |
T146 |
3909 |
3 |
0 |
0 |
T147 |
7726 |
28 |
0 |
0 |
T148 |
13224 |
12 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
5585 |
0 |
0 |
T63 |
100551 |
677 |
0 |
0 |
T108 |
63101 |
344 |
0 |
0 |
T114 |
7183 |
69 |
0 |
0 |
T115 |
3570 |
22 |
0 |
0 |
T117 |
180538 |
440 |
0 |
0 |
T119 |
4181 |
6 |
0 |
0 |
T120 |
11786 |
92 |
0 |
0 |
T146 |
3909 |
60 |
0 |
0 |
T147 |
7726 |
11 |
0 |
0 |
T148 |
13224 |
18 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
5335 |
0 |
0 |
T63 |
100551 |
1002 |
0 |
0 |
T108 |
63101 |
294 |
0 |
0 |
T114 |
7183 |
6 |
0 |
0 |
T117 |
180538 |
434 |
0 |
0 |
T119 |
4181 |
22 |
0 |
0 |
T120 |
11786 |
58 |
0 |
0 |
T146 |
3909 |
50 |
0 |
0 |
T147 |
7726 |
30 |
0 |
0 |
T148 |
13224 |
67 |
0 |
0 |
T149 |
31303 |
267 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
5747 |
0 |
0 |
T63 |
100551 |
718 |
0 |
0 |
T108 |
63101 |
368 |
0 |
0 |
T114 |
7183 |
6 |
0 |
0 |
T117 |
180538 |
447 |
0 |
0 |
T119 |
4181 |
22 |
0 |
0 |
T120 |
11786 |
67 |
0 |
0 |
T146 |
3909 |
56 |
0 |
0 |
T147 |
7726 |
51 |
0 |
0 |
T148 |
13224 |
73 |
0 |
0 |
T149 |
31303 |
232 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
5727 |
0 |
0 |
T63 |
100551 |
533 |
0 |
0 |
T108 |
63101 |
331 |
0 |
0 |
T114 |
7183 |
66 |
0 |
0 |
T117 |
180538 |
448 |
0 |
0 |
T119 |
4181 |
14 |
0 |
0 |
T120 |
11786 |
166 |
0 |
0 |
T122 |
181051 |
406 |
0 |
0 |
T146 |
3909 |
79 |
0 |
0 |
T148 |
13224 |
39 |
0 |
0 |
T149 |
31303 |
236 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
5475 |
0 |
0 |
T63 |
100551 |
668 |
0 |
0 |
T108 |
63101 |
202 |
0 |
0 |
T114 |
7183 |
46 |
0 |
0 |
T115 |
3570 |
19 |
0 |
0 |
T117 |
180538 |
451 |
0 |
0 |
T120 |
11786 |
27 |
0 |
0 |
T146 |
3909 |
50 |
0 |
0 |
T147 |
7726 |
29 |
0 |
0 |
T148 |
13224 |
63 |
0 |
0 |
T149 |
31303 |
234 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
5085 |
0 |
0 |
T63 |
100551 |
627 |
0 |
0 |
T108 |
63101 |
153 |
0 |
0 |
T114 |
7183 |
48 |
0 |
0 |
T115 |
3570 |
19 |
0 |
0 |
T117 |
180538 |
416 |
0 |
0 |
T120 |
11786 |
92 |
0 |
0 |
T146 |
3909 |
57 |
0 |
0 |
T147 |
7726 |
33 |
0 |
0 |
T148 |
13224 |
89 |
0 |
0 |
T149 |
31303 |
213 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
5337 |
0 |
0 |
T63 |
100551 |
640 |
0 |
0 |
T108 |
63101 |
348 |
0 |
0 |
T114 |
7183 |
37 |
0 |
0 |
T115 |
3570 |
1 |
0 |
0 |
T117 |
180538 |
486 |
0 |
0 |
T120 |
11786 |
82 |
0 |
0 |
T122 |
181051 |
446 |
0 |
0 |
T147 |
7726 |
10 |
0 |
0 |
T148 |
13224 |
32 |
0 |
0 |
T149 |
31303 |
220 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
5471 |
0 |
0 |
T63 |
100551 |
840 |
0 |
0 |
T108 |
63101 |
203 |
0 |
0 |
T114 |
7183 |
70 |
0 |
0 |
T115 |
3570 |
26 |
0 |
0 |
T117 |
180538 |
427 |
0 |
0 |
T120 |
11786 |
100 |
0 |
0 |
T146 |
3909 |
64 |
0 |
0 |
T147 |
7726 |
21 |
0 |
0 |
T148 |
13224 |
51 |
0 |
0 |
T149 |
31303 |
246 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
5493 |
0 |
0 |
T63 |
100551 |
658 |
0 |
0 |
T108 |
63101 |
245 |
0 |
0 |
T114 |
7183 |
3 |
0 |
0 |
T117 |
180538 |
427 |
0 |
0 |
T119 |
4181 |
2 |
0 |
0 |
T120 |
11786 |
169 |
0 |
0 |
T146 |
3909 |
61 |
0 |
0 |
T147 |
7726 |
24 |
0 |
0 |
T148 |
13224 |
7 |
0 |
0 |
T149 |
31303 |
387 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
5216 |
0 |
0 |
T63 |
100551 |
697 |
0 |
0 |
T108 |
63101 |
337 |
0 |
0 |
T114 |
7183 |
7 |
0 |
0 |
T117 |
180538 |
493 |
0 |
0 |
T119 |
4181 |
36 |
0 |
0 |
T120 |
11786 |
18 |
0 |
0 |
T146 |
3909 |
37 |
0 |
0 |
T147 |
7726 |
8 |
0 |
0 |
T148 |
13224 |
96 |
0 |
0 |
T149 |
31303 |
271 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
5035 |
0 |
0 |
T63 |
100551 |
586 |
0 |
0 |
T108 |
63101 |
200 |
0 |
0 |
T114 |
7183 |
48 |
0 |
0 |
T115 |
3570 |
18 |
0 |
0 |
T117 |
180538 |
403 |
0 |
0 |
T120 |
11786 |
109 |
0 |
0 |
T146 |
3909 |
3 |
0 |
0 |
T147 |
7726 |
32 |
0 |
0 |
T148 |
13224 |
56 |
0 |
0 |
T149 |
31303 |
190 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
5358 |
0 |
0 |
T63 |
100551 |
580 |
0 |
0 |
T108 |
63101 |
336 |
0 |
0 |
T114 |
7183 |
53 |
0 |
0 |
T117 |
180538 |
450 |
0 |
0 |
T119 |
4181 |
18 |
0 |
0 |
T120 |
11786 |
14 |
0 |
0 |
T146 |
3909 |
1 |
0 |
0 |
T147 |
7726 |
13 |
0 |
0 |
T148 |
13224 |
52 |
0 |
0 |
T149 |
31303 |
196 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
2858 |
0 |
0 |
T63 |
100551 |
154 |
0 |
0 |
T108 |
63101 |
48 |
0 |
0 |
T114 |
7183 |
21 |
0 |
0 |
T117 |
180538 |
443 |
0 |
0 |
T119 |
4181 |
5 |
0 |
0 |
T120 |
11786 |
29 |
0 |
0 |
T146 |
3909 |
5 |
0 |
0 |
T147 |
7726 |
7 |
0 |
0 |
T148 |
13224 |
27 |
0 |
0 |
T149 |
31303 |
34 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
2847 |
0 |
0 |
T63 |
100551 |
149 |
0 |
0 |
T108 |
63101 |
63 |
0 |
0 |
T114 |
7183 |
4 |
0 |
0 |
T117 |
180538 |
465 |
0 |
0 |
T120 |
11786 |
11 |
0 |
0 |
T122 |
181051 |
422 |
0 |
0 |
T146 |
3909 |
10 |
0 |
0 |
T147 |
7726 |
32 |
0 |
0 |
T148 |
13224 |
50 |
0 |
0 |
T149 |
31303 |
42 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
2986 |
0 |
0 |
T63 |
100551 |
160 |
0 |
0 |
T108 |
63101 |
61 |
0 |
0 |
T114 |
7183 |
5 |
0 |
0 |
T115 |
3570 |
8 |
0 |
0 |
T117 |
180538 |
420 |
0 |
0 |
T119 |
4181 |
1 |
0 |
0 |
T120 |
11786 |
22 |
0 |
0 |
T146 |
3909 |
10 |
0 |
0 |
T147 |
7726 |
36 |
0 |
0 |
T148 |
13224 |
96 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
2905 |
0 |
0 |
T63 |
100551 |
145 |
0 |
0 |
T108 |
63101 |
62 |
0 |
0 |
T114 |
7183 |
11 |
0 |
0 |
T115 |
3570 |
2 |
0 |
0 |
T117 |
180538 |
447 |
0 |
0 |
T119 |
4181 |
10 |
0 |
0 |
T120 |
11786 |
10 |
0 |
0 |
T146 |
3909 |
6 |
0 |
0 |
T147 |
7726 |
12 |
0 |
0 |
T148 |
13224 |
42 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
3453 |
0 |
0 |
T63 |
100551 |
290 |
0 |
0 |
T108 |
63101 |
66 |
0 |
0 |
T114 |
7183 |
37 |
0 |
0 |
T115 |
3570 |
6 |
0 |
0 |
T117 |
180538 |
465 |
0 |
0 |
T119 |
4181 |
7 |
0 |
0 |
T120 |
11786 |
46 |
0 |
0 |
T146 |
3909 |
5 |
0 |
0 |
T147 |
7726 |
13 |
0 |
0 |
T148 |
13224 |
33 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
4837 |
0 |
0 |
T14 |
447961 |
31 |
0 |
0 |
T15 |
679151 |
0 |
0 |
0 |
T17 |
0 |
17 |
0 |
0 |
T22 |
0 |
11 |
0 |
0 |
T41 |
192932 |
0 |
0 |
0 |
T87 |
29896 |
0 |
0 |
0 |
T150 |
0 |
36 |
0 |
0 |
T151 |
0 |
46 |
0 |
0 |
T152 |
0 |
24 |
0 |
0 |
T153 |
0 |
59 |
0 |
0 |
T154 |
0 |
44 |
0 |
0 |
T155 |
0 |
8 |
0 |
0 |
T156 |
0 |
6 |
0 |
0 |
T157 |
3119 |
0 |
0 |
0 |
T158 |
156166 |
0 |
0 |
0 |
T159 |
99673 |
0 |
0 |
0 |
T160 |
2867 |
0 |
0 |
0 |
T161 |
321020 |
0 |
0 |
0 |
T162 |
1516 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
3004 |
0 |
0 |
T63 |
100551 |
156 |
0 |
0 |
T108 |
63101 |
41 |
0 |
0 |
T115 |
3570 |
5 |
0 |
0 |
T117 |
180538 |
495 |
0 |
0 |
T120 |
11786 |
9 |
0 |
0 |
T122 |
181051 |
435 |
0 |
0 |
T146 |
3909 |
2 |
0 |
0 |
T147 |
7726 |
29 |
0 |
0 |
T148 |
13224 |
5 |
0 |
0 |
T149 |
31303 |
60 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
2952 |
0 |
0 |
T63 |
100551 |
155 |
0 |
0 |
T108 |
63101 |
60 |
0 |
0 |
T114 |
7183 |
12 |
0 |
0 |
T115 |
3570 |
8 |
0 |
0 |
T117 |
180538 |
412 |
0 |
0 |
T119 |
4181 |
4 |
0 |
0 |
T120 |
11786 |
10 |
0 |
0 |
T146 |
3909 |
2 |
0 |
0 |
T147 |
7726 |
24 |
0 |
0 |
T148 |
13224 |
49 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
2758 |
0 |
0 |
T63 |
100551 |
93 |
0 |
0 |
T108 |
63101 |
45 |
0 |
0 |
T114 |
7183 |
5 |
0 |
0 |
T117 |
180538 |
401 |
0 |
0 |
T119 |
4181 |
1 |
0 |
0 |
T120 |
11786 |
13 |
0 |
0 |
T146 |
3909 |
1 |
0 |
0 |
T147 |
7726 |
17 |
0 |
0 |
T148 |
13224 |
32 |
0 |
0 |
T149 |
31303 |
50 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
2684 |
0 |
0 |
T63 |
100551 |
103 |
0 |
0 |
T108 |
63101 |
44 |
0 |
0 |
T114 |
7183 |
7 |
0 |
0 |
T115 |
3570 |
6 |
0 |
0 |
T117 |
180538 |
424 |
0 |
0 |
T119 |
4181 |
3 |
0 |
0 |
T120 |
11786 |
11 |
0 |
0 |
T146 |
3909 |
8 |
0 |
0 |
T147 |
7726 |
8 |
0 |
0 |
T148 |
13224 |
9 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
2868 |
0 |
0 |
T63 |
100551 |
118 |
0 |
0 |
T108 |
63101 |
40 |
0 |
0 |
T114 |
7183 |
5 |
0 |
0 |
T117 |
180538 |
491 |
0 |
0 |
T119 |
4181 |
10 |
0 |
0 |
T120 |
11786 |
15 |
0 |
0 |
T146 |
3909 |
3 |
0 |
0 |
T147 |
7726 |
35 |
0 |
0 |
T148 |
13224 |
37 |
0 |
0 |
T149 |
31303 |
14 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
2830 |
0 |
0 |
T63 |
100551 |
105 |
0 |
0 |
T108 |
63101 |
45 |
0 |
0 |
T114 |
7183 |
15 |
0 |
0 |
T115 |
3570 |
2 |
0 |
0 |
T117 |
180538 |
452 |
0 |
0 |
T120 |
11786 |
19 |
0 |
0 |
T146 |
3909 |
2 |
0 |
0 |
T147 |
7726 |
22 |
0 |
0 |
T148 |
13224 |
37 |
0 |
0 |
T149 |
31303 |
41 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
3449 |
0 |
0 |
T63 |
100551 |
299 |
0 |
0 |
T108 |
63101 |
79 |
0 |
0 |
T114 |
7183 |
23 |
0 |
0 |
T115 |
3570 |
5 |
0 |
0 |
T117 |
180538 |
483 |
0 |
0 |
T119 |
4181 |
21 |
0 |
0 |
T120 |
11786 |
30 |
0 |
0 |
T146 |
3909 |
3 |
0 |
0 |
T147 |
7726 |
36 |
0 |
0 |
T148 |
13224 |
13 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
2757 |
0 |
0 |
T63 |
100551 |
115 |
0 |
0 |
T108 |
63101 |
53 |
0 |
0 |
T114 |
7183 |
2 |
0 |
0 |
T115 |
3570 |
9 |
0 |
0 |
T117 |
180538 |
442 |
0 |
0 |
T120 |
11786 |
9 |
0 |
0 |
T146 |
3909 |
6 |
0 |
0 |
T147 |
7726 |
16 |
0 |
0 |
T148 |
13224 |
61 |
0 |
0 |
T149 |
31303 |
34 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
3620 |
0 |
0 |
T63 |
100551 |
310 |
0 |
0 |
T108 |
63101 |
113 |
0 |
0 |
T114 |
7183 |
34 |
0 |
0 |
T115 |
3570 |
12 |
0 |
0 |
T117 |
180538 |
518 |
0 |
0 |
T119 |
4181 |
9 |
0 |
0 |
T120 |
11786 |
17 |
0 |
0 |
T146 |
3909 |
1 |
0 |
0 |
T147 |
7726 |
23 |
0 |
0 |
T148 |
13224 |
60 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
3088 |
0 |
0 |
T63 |
100551 |
184 |
0 |
0 |
T108 |
63101 |
91 |
0 |
0 |
T114 |
7183 |
8 |
0 |
0 |
T115 |
3570 |
3 |
0 |
0 |
T117 |
180538 |
477 |
0 |
0 |
T120 |
11786 |
17 |
0 |
0 |
T146 |
3909 |
3 |
0 |
0 |
T147 |
7726 |
42 |
0 |
0 |
T148 |
13224 |
64 |
0 |
0 |
T149 |
31303 |
64 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
2787 |
0 |
0 |
T63 |
100551 |
139 |
0 |
0 |
T108 |
63101 |
51 |
0 |
0 |
T114 |
7183 |
5 |
0 |
0 |
T117 |
180538 |
460 |
0 |
0 |
T119 |
4181 |
8 |
0 |
0 |
T120 |
11786 |
11 |
0 |
0 |
T146 |
3909 |
8 |
0 |
0 |
T147 |
7726 |
28 |
0 |
0 |
T148 |
13224 |
50 |
0 |
0 |
T149 |
31303 |
42 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
2665 |
0 |
0 |
T63 |
100551 |
83 |
0 |
0 |
T108 |
63101 |
36 |
0 |
0 |
T114 |
7183 |
4 |
0 |
0 |
T115 |
3570 |
8 |
0 |
0 |
T117 |
180538 |
463 |
0 |
0 |
T120 |
11786 |
7 |
0 |
0 |
T122 |
181051 |
458 |
0 |
0 |
T147 |
7726 |
9 |
0 |
0 |
T148 |
13224 |
30 |
0 |
0 |
T149 |
31303 |
51 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
2660 |
0 |
0 |
T63 |
100551 |
106 |
0 |
0 |
T108 |
63101 |
31 |
0 |
0 |
T114 |
7183 |
2 |
0 |
0 |
T117 |
180538 |
426 |
0 |
0 |
T120 |
11786 |
12 |
0 |
0 |
T122 |
181051 |
475 |
0 |
0 |
T146 |
3909 |
9 |
0 |
0 |
T147 |
7726 |
31 |
0 |
0 |
T148 |
13224 |
29 |
0 |
0 |
T149 |
31303 |
35 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
2742 |
0 |
0 |
T63 |
100551 |
108 |
0 |
0 |
T108 |
63101 |
31 |
0 |
0 |
T114 |
7183 |
7 |
0 |
0 |
T117 |
180538 |
452 |
0 |
0 |
T119 |
4181 |
6 |
0 |
0 |
T120 |
11786 |
7 |
0 |
0 |
T146 |
3909 |
4 |
0 |
0 |
T147 |
7726 |
23 |
0 |
0 |
T148 |
13224 |
61 |
0 |
0 |
T149 |
31303 |
44 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
2715 |
0 |
0 |
T63 |
100551 |
106 |
0 |
0 |
T108 |
63101 |
39 |
0 |
0 |
T114 |
7183 |
16 |
0 |
0 |
T117 |
180538 |
455 |
0 |
0 |
T119 |
4181 |
3 |
0 |
0 |
T120 |
11786 |
12 |
0 |
0 |
T122 |
181051 |
436 |
0 |
0 |
T147 |
7726 |
42 |
0 |
0 |
T148 |
13224 |
58 |
0 |
0 |
T149 |
31303 |
32 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
488260216 |
2635 |
0 |
0 |
T63 |
100551 |
82 |
0 |
0 |
T108 |
63101 |
54 |
0 |
0 |
T114 |
7183 |
5 |
0 |
0 |
T115 |
3570 |
3 |
0 |
0 |
T117 |
180538 |
396 |
0 |
0 |
T119 |
4181 |
1 |
0 |
0 |
T120 |
11786 |
22 |
0 |
0 |
T146 |
3909 |
3 |
0 |
0 |
T147 |
7726 |
55 |
0 |
0 |
T148 |
13224 |
41 |
0 |
0 |