Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3509602	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4083175

1

T1

1862

T2

5769

T3

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4235481	1			T1	5110		T2	9625		T3	1
values[0x0]	1676952	1			T1	891		T2	447		T3	9
values[0x1]	1680344	1			T1	884		T2	444		T3	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2491024	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5101753

1

T1

3470

T2

6726

T3

9

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	25690	1			T1	45		T6	56		T7	5
valid_sources[0x01]	30036	1			T1	4		T4	39		T6	51
valid_sources[0x02]	28315	1			T1	69		T7	2		T9	25
valid_sources[0x03]	36530	1			T1	38		T6	1		T7	19
valid_sources[0x04]	29367	1			T1	11		T6	2		T7	1
valid_sources[0x05]	29692	1			T1	28		T5	15		T7	6
valid_sources[0x06]	28399	1			T1	28		T4	23		T6	168
valid_sources[0x07]	32336	1			T1	26		T7	4		T9	42
valid_sources[0x08]	28844	1			T1	48		T7	5		T9	37
valid_sources[0x09]	28786	1			T1	13		T6	102		T7	6
valid_sources[0x0a]	27416	1			T1	1		T7	6		T9	37
valid_sources[0x0b]	28193	1			T1	6		T5	7		T6	56
valid_sources[0x0c]	25878	1			T1	29		T6	91		T7	4
valid_sources[0x0d]	35980	1			T1	42		T6	1316		T7	4
valid_sources[0x0e]	28831	1			T1	12		T3	1		T6	1
valid_sources[0x0f]	27867	1			T1	2		T7	12		T9	40
valid_sources[0x10]	29477	1			T1	9		T9	19		T10	61
valid_sources[0x11]	43730	1			T1	1		T6	5		T7	5
valid_sources[0x12]	26479	1			T1	19		T6	2		T7	5
valid_sources[0x13]	28576	1			T1	1		T6	2		T7	6
valid_sources[0x14]	29556	1			T1	25		T6	3		T7	8
valid_sources[0x15]	29805	1			T1	33		T6	2		T7	3
valid_sources[0x16]	28650	1			T1	13		T5	9		T6	10
valid_sources[0x17]	28010	1			T1	12		T6	203		T7	1
valid_sources[0x18]	27803	1			T1	12		T7	4		T9	33
valid_sources[0x19]	29067	1			T1	7		T7	4		T9	44
valid_sources[0x1a]	29660	1			T1	18		T7	6		T9	35
valid_sources[0x1b]	30169	1			T1	11		T5	62		T6	1955
valid_sources[0x1c]	38853	1			T1	55		T6	77		T7	3
valid_sources[0x1d]	32602	1			T1	22		T5	14		T6	474
valid_sources[0x1e]	31374	1			T6	96		T7	3		T9	42
valid_sources[0x1f]	28423	1			T1	67		T6	1		T7	3
valid_sources[0x20]	29103	1			T1	61		T4	2		T5	8
valid_sources[0x21]	27679	1			T1	53		T6	2		T7	12
valid_sources[0x22]	31271	1			T1	31		T7	2		T9	35
valid_sources[0x23]	30242	1			T1	23		T6	2		T7	9
valid_sources[0x24]	31448	1			T1	33		T6	4		T7	3
valid_sources[0x25]	28301	1			T1	19		T4	50		T6	46
valid_sources[0x26]	26856	1			T1	25		T5	5		T7	2
valid_sources[0x27]	29660	1			T1	3		T4	35		T7	3
valid_sources[0x28]	29894	1			T1	37		T4	8		T6	92
valid_sources[0x29]	26354	1			T1	34		T6	7		T7	13
valid_sources[0x2a]	28150	1			T1	31		T5	8		T6	7
valid_sources[0x2b]	32399	1			T1	13		T6	1		T7	3
valid_sources[0x2c]	30781	1			T1	55		T5	37		T6	27
valid_sources[0x2d]	29967	1			T1	43		T6	1		T7	8
valid_sources[0x2e]	31230	1			T1	26		T6	9		T7	7
valid_sources[0x2f]	35304	1			T4	20		T6	30		T7	7
valid_sources[0x30]	29071	1			T6	12		T7	2		T9	33
valid_sources[0x31]	27678	1			T1	42		T6	12		T7	4
valid_sources[0x32]	28695	1			T1	5		T4	24		T6	4
valid_sources[0x33]	27599	1			T1	32		T6	7		T7	1
valid_sources[0x34]	26003	1			T1	20		T6	44		T7	7
valid_sources[0x35]	27936	1			T1	21		T6	48		T7	4
valid_sources[0x36]	28651	1			T1	55		T4	10		T6	39
valid_sources[0x37]	28831	1			T1	46		T6	24		T7	15
valid_sources[0x38]	27686	1			T1	57		T5	23		T6	5
valid_sources[0x39]	29433	1			T1	45		T7	5		T9	31
valid_sources[0x3a]	28840	1			T1	37		T6	66		T7	8
valid_sources[0x3b]	32721	1			T1	8		T5	60		T6	69
valid_sources[0x3c]	25617	1			T1	22		T5	5		T6	9
valid_sources[0x3d]	27688	1			T1	13		T9	33		T10	66
valid_sources[0x3e]	26484	1			T1	29		T7	7		T9	38
valid_sources[0x3f]	30650	1			T1	37		T7	1		T9	42
valid_sources[0x40]	28619	1			T1	9		T6	1		T7	5
valid_sources[0x41]	30086	1			T1	44		T6	21		T7	4
valid_sources[0x42]	28071	1			T1	10		T7	3		T9	33
valid_sources[0x43]	33119	1			T1	23		T3	2		T5	26
valid_sources[0x44]	27090	1			T1	37		T6	48		T7	1
valid_sources[0x45]	33335	1			T1	7		T6	16		T7	4
valid_sources[0x46]	26170	1			T1	22		T6	20		T7	5
valid_sources[0x47]	29930	1			T1	16		T4	39		T6	70
valid_sources[0x48]	29837	1			T1	59		T5	15		T6	71
valid_sources[0x49]	30285	1			T1	38		T6	1		T7	4
valid_sources[0x4a]	31562	1			T1	21		T4	4		T5	2
valid_sources[0x4b]	33877	1			T1	26		T6	2		T7	9
valid_sources[0x4c]	28994	1			T1	33		T6	2		T7	7
valid_sources[0x4d]	26470	1			T1	13		T7	4		T9	24
valid_sources[0x4e]	27763	1			T1	7		T7	3		T9	36
valid_sources[0x4f]	29058	1			T1	54		T7	2		T9	35
valid_sources[0x50]	36267	1			T1	78		T3	1		T4	74
valid_sources[0x51]	29323	1			T1	21		T6	31		T7	8
valid_sources[0x52]	29771	1			T1	22		T4	8		T6	131
valid_sources[0x53]	31922	1			T1	27		T6	442		T7	3
valid_sources[0x54]	28794	1			T1	47		T6	46		T7	1
valid_sources[0x55]	27638	1			T1	63		T6	1		T7	2
valid_sources[0x56]	27861	1			T1	30		T6	35		T7	5
valid_sources[0x57]	31801	1			T1	47		T6	83		T7	5
valid_sources[0x58]	31685	1			T1	70		T7	3		T9	38
valid_sources[0x59]	29259	1			T1	18		T5	50		T6	1
valid_sources[0x5a]	29015	1			T1	30		T6	83		T7	1
valid_sources[0x5b]	31762	1			T1	20		T6	185		T7	8
valid_sources[0x5c]	28176	1			T1	10		T6	5		T7	2
valid_sources[0x5d]	28711	1			T1	12		T7	3		T9	40
valid_sources[0x5e]	28558	1			T1	18		T6	155		T7	2
valid_sources[0x5f]	27631	1			T1	18		T6	1		T7	6
valid_sources[0x60]	26411	1			T1	6		T6	34		T7	8
valid_sources[0x61]	29174	1			T1	21		T6	98		T7	4
valid_sources[0x62]	27070	1			T1	56		T6	1		T7	6
valid_sources[0x63]	27380	1			T1	51		T6	265		T7	7
valid_sources[0x64]	37578	1			T1	4		T6	4		T7	10
valid_sources[0x65]	27076	1			T6	1		T7	3		T9	34
valid_sources[0x66]	28740	1			T1	48		T6	4		T7	5
valid_sources[0x67]	27641	1			T1	22		T7	4		T9	34
valid_sources[0x68]	27300	1			T1	55		T4	2		T7	2
valid_sources[0x69]	26127	1			T1	23		T6	20		T7	2
valid_sources[0x6a]	24645	1			T1	16		T6	1		T7	3
valid_sources[0x6b]	33609	1			T1	44		T6	1		T7	4
valid_sources[0x6c]	27279	1			T1	30		T6	12		T7	1
valid_sources[0x6d]	36299	1			T1	9		T6	17		T7	6
valid_sources[0x6e]	30773	1			T1	18		T4	92		T6	2
valid_sources[0x6f]	33551	1			T1	7		T4	10		T6	2
valid_sources[0x70]	29654	1			T1	26		T7	6		T9	27
valid_sources[0x71]	29436	1			T1	27		T6	123		T9	31
valid_sources[0x72]	29791	1			T1	13		T5	1		T6	17
valid_sources[0x73]	27775	1			T1	26		T6	2		T7	1
valid_sources[0x74]	28568	1			T1	26		T6	32		T7	8
valid_sources[0x75]	29327	1			T1	15		T7	5		T9	39
valid_sources[0x76]	29001	1			T1	1		T6	2		T7	4
valid_sources[0x77]	28523	1			T1	14		T6	3		T7	2
valid_sources[0x78]	28617	1			T1	9		T5	31		T6	1
valid_sources[0x79]	27495	1			T1	39		T3	1		T6	2
valid_sources[0x7a]	28209	1			T1	57		T6	387		T7	4
valid_sources[0x7b]	27805	1			T1	33		T5	7		T6	52
valid_sources[0x7c]	30760	1			T1	34		T5	47		T6	9
valid_sources[0x7d]	29645	1			T1	13		T5	21		T6	473
valid_sources[0x7e]	31711	1			T1	35		T7	11		T9	32
valid_sources[0x7f]	36571	1			T1	30		T6	5		T7	11
valid_sources[0x80]	30892	1			T1	5		T4	63		T6	118

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1044670

1

T1

522

T2

4887

T3

1

values[0x0]

all_enables

biggest_size

1529667

1

T1

681

T2

446

T3

3

values[0x1]

all_enables

biggest_size

1508838

1

T1

659

T2

436

T3

3