Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3531743

1

T1

5023

T2

4747

T3

10

full_word

4084416

1

T1

1862

T2

5769

T3

7

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7615809	1			T1	6885		T2	10516		T3	17
auto[TlIntgErrCmd]	123	1			T58	8		T86	2		T87	1
auto[TlIntgErrData]	112	1			T58	6		T86	3		T87	6
auto[TlIntgErrBoth]	115	1			T58	6		T86	5		T87	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4238926

1

T1

5110

T2

9625

T3

1

auto[1]

3377233

1

T1

1775

T2

891

T3

16

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3193838	1			T1	4588		T2	4738		T4	2
auto[TlIntgErrNone]	partial	auto[1]	337580	1			T1	435		T2	9		T3	10
auto[TlIntgErrNone]	full_word	auto[0]	1044937	1			T1	522		T2	4887		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	3039454	1			T1	1340		T2	882		T3	6
auto[TlIntgErrCmd]	partial	auto[0]	52	1			T58	3		T106	5		T160	2
auto[TlIntgErrCmd]	partial	auto[1]	65	1			T58	4		T86	2		T87	1
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T162	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T58	1		T159	1		T97	1
auto[TlIntgErrData]	partial	auto[0]	48	1			T58	2		T86	1		T87	3
auto[TlIntgErrData]	partial	auto[1]	55	1			T58	4		T86	2		T87	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T163	1		T164	2		T165	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T160	2		T161	1		T166	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T58	3		T106	4		T159	3
auto[TlIntgErrBoth]	partial	auto[1]	64	1			T58	2		T86	5		T87	3
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T159	1		T167	1		T168	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T58	1		T159	1		T97	1