Unified Coverage Report :: Module :: prim_generic_ram_1r1w

Module : prim_generic_ram_1r1w

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1r1w

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	601565310	3141464	0	0
gen_wmask[1].MaskCheckPortA_A	601565310	3141464	0	0
gen_wmask[2].MaskCheckPortA_A	601565310	3141464	0	0
gen_wmask[3].MaskCheckPortA_A	601565310	3141464	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601565310	3141464	0	0
T1	436126	2386	0	0
T2	157922	832	0	0
T3	1235	0	0	0
T4	8897	832	0	0
T5	2768	832	0	0
T6	1148157	21119	0	0
T7	32680	832	0	0
T8	113907	832	0	0
T9	661873	6701	0	0
T10	690827	7832	0	0
T12	14981	832	0	0
T14	250071	390	0	0
T15	515905	4440	0	0
T16	0	160	0	0
T25	0	1886	0	0
T26	0	962	0	0
T32	0	258	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601565310	3141464	0	0
T1	436126	2386	0	0
T2	157922	832	0	0
T3	1235	0	0	0
T4	8897	832	0	0
T5	2768	832	0	0
T6	1148157	21119	0	0
T7	32680	832	0	0
T8	113907	832	0	0
T9	661873	6701	0	0
T10	690827	7832	0	0
T12	14981	832	0	0
T14	250071	390	0	0
T15	515905	4440	0	0
T16	0	160	0	0
T25	0	1886	0	0
T26	0	962	0	0
T32	0	258	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601565310	3141464	0	0
T1	436126	2386	0	0
T2	157922	832	0	0
T3	1235	0	0	0
T4	8897	832	0	0
T5	2768	832	0	0
T6	1148157	21119	0	0
T7	32680	832	0	0
T8	113907	832	0	0
T9	661873	6701	0	0
T10	690827	7832	0	0
T12	14981	832	0	0
T14	250071	390	0	0
T15	515905	4440	0	0
T16	0	160	0	0
T25	0	1886	0	0
T26	0	962	0	0
T32	0	258	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601565310	3141464	0	0
T1	436126	2386	0	0
T2	157922	832	0	0
T3	1235	0	0	0
T4	8897	832	0	0
T5	2768	832	0	0
T6	1148157	21119	0	0
T7	32680	832	0	0
T8	113907	832	0	0
T9	661873	6701	0	0
T10	690827	7832	0	0
T12	14981	832	0	0
T14	250071	390	0	0
T15	515905	4440	0	0
T16	0	160	0	0
T25	0	1886	0	0
T26	0	962	0	0
T32	0	258	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			==> MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T6

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	456230764	1968310	0	0
gen_wmask[1].MaskCheckPortA_A	456230764	1968310	0	0
gen_wmask[2].MaskCheckPortA_A	456230764	1968310	0	0
gen_wmask[3].MaskCheckPortA_A	456230764	1968310	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456230764	1968310	0	0
T1	381620	763	0	0
T2	135794	832	0	0
T3	1235	0	0	0
T4	8897	832	0	0
T5	2768	832	0	0
T6	436975	9352	0	0
T7	20901	832	0	0
T8	87390	832	0	0
T9	172323	3606	0	0
T10	351139	3898	0	0
T12	0	832	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456230764	1968310	0	0
T1	381620	763	0	0
T2	135794	832	0	0
T3	1235	0	0	0
T4	8897	832	0	0
T5	2768	832	0	0
T6	436975	9352	0	0
T7	20901	832	0	0
T8	87390	832	0	0
T9	172323	3606	0	0
T10	351139	3898	0	0
T12	0	832	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456230764	1968310	0	0
T1	381620	763	0	0
T2	135794	832	0	0
T3	1235	0	0	0
T4	8897	832	0	0
T5	2768	832	0	0
T6	436975	9352	0	0
T7	20901	832	0	0
T8	87390	832	0	0
T9	172323	3606	0	0
T10	351139	3898	0	0
T12	0	832	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456230764	1968310	0	0
T1	381620	763	0	0
T2	135794	832	0	0
T3	1235	0	0	0
T4	8897	832	0	0
T5	2768	832	0	0
T6	436975	9352	0	0
T7	20901	832	0	0
T8	87390	832	0	0
T9	172323	3606	0	0
T10	351139	3898	0	0
T12	0	832	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T9
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	145334546	1173154	0	0
gen_wmask[1].MaskCheckPortA_A	145334546	1173154	0	0
gen_wmask[2].MaskCheckPortA_A	145334546	1173154	0	0
gen_wmask[3].MaskCheckPortA_A	145334546	1173154	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145334546	1173154	0	0
T1	54506	1623	0	0
T2	22128	0	0	0
T6	711182	11767	0	0
T7	11779	0	0	0
T8	26517	0	0	0
T9	489550	3095	0	0
T10	339688	3934	0	0
T12	14981	0	0	0
T14	250071	390	0	0
T15	515905	4440	0	0
T16	0	160	0	0
T25	0	1886	0	0
T26	0	962	0	0
T32	0	258	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145334546	1173154	0	0
T1	54506	1623	0	0
T2	22128	0	0	0
T6	711182	11767	0	0
T7	11779	0	0	0
T8	26517	0	0	0
T9	489550	3095	0	0
T10	339688	3934	0	0
T12	14981	0	0	0
T14	250071	390	0	0
T15	515905	4440	0	0
T16	0	160	0	0
T25	0	1886	0	0
T26	0	962	0	0
T32	0	258	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145334546	1173154	0	0
T1	54506	1623	0	0
T2	22128	0	0	0
T6	711182	11767	0	0
T7	11779	0	0	0
T8	26517	0	0	0
T9	489550	3095	0	0
T10	339688	3934	0	0
T12	14981	0	0	0
T14	250071	390	0	0
T15	515905	4440	0	0
T16	0	160	0	0
T25	0	1886	0	0
T26	0	962	0	0
T32	0	258	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145334546	1173154	0	0
T1	54506	1623	0	0
T2	22128	0	0	0
T6	711182	11767	0	0
T7	11779	0	0	0
T8	26517	0	0	0
T9	489550	3095	0	0
T10	339688	3934	0	0
T12	14981	0	0	0
T14	250071	390	0	0
T15	515905	4440	0	0
T16	0	160	0	0
T25	0	1886	0	0
T26	0	962	0	0
T32	0	258	0	0