Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T6,T9
1	0	Covered	T1,T6,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T9
1	0	Unreachable
1	1	Covered	T1,T6,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T9,T10

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T9,T10
1	0	Covered	T6,T9,T10

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T7
1	0	Unreachable
1	1	Covered	T6,T9,T10

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T6,T9
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	746899856	600178543	0	0
CheckNGreaterZero_A	2868	2868	0	0
GntImpliesReady_A	746899856	3511516	0	0
GntImpliesValid_A	746899856	3511516	0	0
GrantKnown_A	746899856	600178543	0	0
IdxKnown_A	746899856	600178543	0	0
IndexIsCorrect_A	746899856	3511516	0	0
LockArbDecision_A	746899856	0	0	0
NoReadyValidNoGrant_A	746899856	0	0	0
ReadyAndValidImplyGrant_A	746899856	3511516	0	0
ReqAndReadyImplyGrant_A	746899856	3511516	0	0
ReqImpliesValid_A	746899856	3511516	0	0
ReqStaysHighUntilGranted0_M	746899856	0	0	0
RoundRobin_A	746899856	4	0	956
ValidKnown_A	746899856	600178543	0	0
gen_data_port_assertion.DataFlow_A	746899856	3511516	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	746899856	600178543	0	0
T1	436126	434692	0	0
T2	180050	157824	0	0
T3	1235	1152	0	0
T4	8897	8818	0	0
T5	2768	2674	0	0
T6	1859339	1143751	0	0
T7	44459	32235	0	0
T8	140424	113767	0	0
T9	1151423	658400	0	0
T10	1030515	685444	0	0
T12	29962	14529	0	0
T14	500142	247846	0	0
T15	1031810	506299	0	0
T16	1948	1920	0	0
T17	0	33552	0	0
T25	0	64160	0	0
T26	0	122752	0	0
T27	0	2920	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2868	2868	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	746899856	3511516	0	0
T1	436126	3643	0	0
T2	157922	832	0	0
T3	1235	0	0	0
T4	8897	832	0	0
T5	2768	832	0	0
T6	1859339	22161	0	0
T7	44459	832	0	0
T8	140424	832	0	0
T9	1151423	8669	0	0
T10	1030515	10367	0	0
T12	29962	832	0	0
T14	500142	420	0	0
T15	1031810	6377	0	0
T16	1948	175	0	0
T17	34030	0	0	0
T25	0	2611	0	0
T26	0	1600	0	0
T27	0	276	0	0
T32	0	258	0	0
T36	0	520	0	0
T38	0	9929	0	0
T39	0	6268	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	746899856	3511516	0	0
T1	436126	3643	0	0
T2	157922	832	0	0
T3	1235	0	0	0
T4	8897	832	0	0
T5	2768	832	0	0
T6	1859339	22161	0	0
T7	44459	832	0	0
T8	140424	832	0	0
T9	1151423	8669	0	0
T10	1030515	10367	0	0
T12	29962	832	0	0
T14	500142	420	0	0
T15	1031810	6377	0	0
T16	1948	175	0	0
T17	34030	0	0	0
T25	0	2611	0	0
T26	0	1600	0	0
T27	0	276	0	0
T32	0	258	0	0
T36	0	520	0	0
T38	0	9929	0	0
T39	0	6268	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	746899856	600178543	0	0
T1	436126	434692	0	0
T2	180050	157824	0	0
T3	1235	1152	0	0
T4	8897	8818	0	0
T5	2768	2674	0	0
T6	1859339	1143751	0	0
T7	44459	32235	0	0
T8	140424	113767	0	0
T9	1151423	658400	0	0
T10	1030515	685444	0	0
T12	29962	14529	0	0
T14	500142	247846	0	0
T15	1031810	506299	0	0
T16	1948	1920	0	0
T17	0	33552	0	0
T25	0	64160	0	0
T26	0	122752	0	0
T27	0	2920	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	746899856	600178543	0	0
T1	436126	434692	0	0
T2	180050	157824	0	0
T3	1235	1152	0	0
T4	8897	8818	0	0
T5	2768	2674	0	0
T6	1859339	1143751	0	0
T7	44459	32235	0	0
T8	140424	113767	0	0
T9	1151423	658400	0	0
T10	1030515	685444	0	0
T12	29962	14529	0	0
T14	500142	247846	0	0
T15	1031810	506299	0	0
T16	1948	1920	0	0
T17	0	33552	0	0
T25	0	64160	0	0
T26	0	122752	0	0
T27	0	2920	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	746899856	3511516	0	0
T1	436126	3643	0	0
T2	157922	832	0	0
T3	1235	0	0	0
T4	8897	832	0	0
T5	2768	832	0	0
T6	1859339	22161	0	0
T7	44459	832	0	0
T8	140424	832	0	0
T9	1151423	8669	0	0
T10	1030515	10367	0	0
T12	29962	832	0	0
T14	500142	420	0	0
T15	1031810	6377	0	0
T16	1948	175	0	0
T17	34030	0	0	0
T25	0	2611	0	0
T26	0	1600	0	0
T27	0	276	0	0
T32	0	258	0	0
T36	0	520	0	0
T38	0	9929	0	0
T39	0	6268	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	746899856	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	746899856	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	746899856	3511516	0	0
T1	436126	3643	0	0
T2	157922	832	0	0
T3	1235	0	0	0
T4	8897	832	0	0
T5	2768	832	0	0
T6	1859339	22161	0	0
T7	44459	832	0	0
T8	140424	832	0	0
T9	1151423	8669	0	0
T10	1030515	10367	0	0
T12	29962	832	0	0
T14	500142	420	0	0
T15	1031810	6377	0	0
T16	1948	175	0	0
T17	34030	0	0	0
T25	0	2611	0	0
T26	0	1600	0	0
T27	0	276	0	0
T32	0	258	0	0
T36	0	520	0	0
T38	0	9929	0	0
T39	0	6268	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	746899856	3511516	0	0
T1	436126	3643	0	0
T2	157922	832	0	0
T3	1235	0	0	0
T4	8897	832	0	0
T5	2768	832	0	0
T6	1859339	22161	0	0
T7	44459	832	0	0
T8	140424	832	0	0
T9	1151423	8669	0	0
T10	1030515	10367	0	0
T12	29962	832	0	0
T14	500142	420	0	0
T15	1031810	6377	0	0
T16	1948	175	0	0
T17	34030	0	0	0
T25	0	2611	0	0
T26	0	1600	0	0
T27	0	276	0	0
T32	0	258	0	0
T36	0	520	0	0
T38	0	9929	0	0
T39	0	6268	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	746899856	3511516	0	0
T1	436126	3643	0	0
T2	157922	832	0	0
T3	1235	0	0	0
T4	8897	832	0	0
T5	2768	832	0	0
T6	1859339	22161	0	0
T7	44459	832	0	0
T8	140424	832	0	0
T9	1151423	8669	0	0
T10	1030515	10367	0	0
T12	29962	832	0	0
T14	500142	420	0	0
T15	1031810	6377	0	0
T16	1948	175	0	0
T17	34030	0	0	0
T25	0	2611	0	0
T26	0	1600	0	0
T27	0	276	0	0
T32	0	258	0	0
T36	0	520	0	0
T38	0	9929	0	0
T39	0	6268	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	746899856	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	746899856	4	0	956
T23	764557	1	0	1
T24	112151	0	0	1
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	1040	0	0	1
T46	672936	0	0	1
T47	801327	0	0	1
T48	184046	0	0	1
T49	3151	0	0	1
T50	284989	0	0	1
T51	91549	0	0	1
T52	880	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	746899856	600178543	0	0
T1	436126	434692	0	0
T2	180050	157824	0	0
T3	1235	1152	0	0
T4	8897	8818	0	0
T5	2768	2674	0	0
T6	1859339	1143751	0	0
T7	44459	32235	0	0
T8	140424	113767	0	0
T9	1151423	658400	0	0
T10	1030515	685444	0	0
T12	29962	14529	0	0
T14	500142	247846	0	0
T15	1031810	506299	0	0
T16	1948	1920	0	0
T17	0	33552	0	0
T25	0	64160	0	0
T26	0	122752	0	0
T27	0	2920	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	746899856	3511516	0	0
T1	436126	3643	0	0
T2	157922	832	0	0
T3	1235	0	0	0
T4	8897	832	0	0
T5	2768	832	0	0
T6	1859339	22161	0	0
T7	44459	832	0	0
T8	140424	832	0	0
T9	1151423	8669	0	0
T10	1030515	10367	0	0
T12	29962	832	0	0
T14	500142	420	0	0
T15	1031810	6377	0	0
T16	1948	175	0	0
T17	34030	0	0	0
T25	0	2611	0	0
T26	0	1600	0	0
T27	0	276	0	0
T32	0	258	0	0
T36	0	520	0	0
T38	0	9929	0	0
T39	0	6268	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T6,T9
1	0	Covered	T1,T6,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T9
1	0	Unreachable
1	1	Covered	T1,T6,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T6,T9
0	0	1	Unreachable
0	0	0	Covered	T1,T6,T9

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	145334546	27987302	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	145334546	610032	0	0
GntImpliesValid_A	145334546	610032	0	0
GrantKnown_A	145334546	27987302	0	0
IdxKnown_A	145334546	27987302	0	0
IndexIsCorrect_A	145334546	610032	0	0
LockArbDecision_A	145334546	0	0	0
NoReadyValidNoGrant_A	145334546	0	0	0
ReadyAndValidImplyGrant_A	145334546	610032	0	0
ReqAndReadyImplyGrant_A	145334546	610032	0	0
ReqImpliesValid_A	145334546	610032	0	0
ReqStaysHighUntilGranted0_M	145334546	0	0	0
RoundRobin_A	145334546	0	0	0
ValidKnown_A	145334546	27987302	0	0
gen_data_port_assertion.DataFlow_A	145334546	610032	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145334546	27987302	0	0
T1	54506	53144	0	0
T2	22128	0	0	0
T6	711182	10304	0	0
T7	11779	0	0	0
T8	26517	0	0	0
T9	489550	233448	0	0
T10	339688	187160	0	0
T12	14981	0	0	0
T14	250071	26064	0	0
T15	515905	162688	0	0
T16	0	1920	0	0
T25	0	64160	0	0
T26	0	122752	0	0
T27	0	2920	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145334546	610032	0	0
T1	54506	2458	0	0
T2	22128	0	0	0
T6	711182	315	0	0
T7	11779	0	0	0
T8	26517	0	0	0
T9	489550	3574	0	0
T10	339688	5327	0	0
T12	14981	0	0	0
T14	250071	318	0	0
T15	515905	6112	0	0
T16	0	175	0	0
T25	0	2071	0	0
T26	0	1600	0	0
T27	0	276	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145334546	610032	0	0
T1	54506	2458	0	0
T2	22128	0	0	0
T6	711182	315	0	0
T7	11779	0	0	0
T8	26517	0	0	0
T9	489550	3574	0	0
T10	339688	5327	0	0
T12	14981	0	0	0
T14	250071	318	0	0
T15	515905	6112	0	0
T16	0	175	0	0
T25	0	2071	0	0
T26	0	1600	0	0
T27	0	276	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145334546	27987302	0	0
T1	54506	53144	0	0
T2	22128	0	0	0
T6	711182	10304	0	0
T7	11779	0	0	0
T8	26517	0	0	0
T9	489550	233448	0	0
T10	339688	187160	0	0
T12	14981	0	0	0
T14	250071	26064	0	0
T15	515905	162688	0	0
T16	0	1920	0	0
T25	0	64160	0	0
T26	0	122752	0	0
T27	0	2920	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145334546	27987302	0	0
T1	54506	53144	0	0
T2	22128	0	0	0
T6	711182	10304	0	0
T7	11779	0	0	0
T8	26517	0	0	0
T9	489550	233448	0	0
T10	339688	187160	0	0
T12	14981	0	0	0
T14	250071	26064	0	0
T15	515905	162688	0	0
T16	0	1920	0	0
T25	0	64160	0	0
T26	0	122752	0	0
T27	0	2920	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145334546	610032	0	0
T1	54506	2458	0	0
T2	22128	0	0	0
T6	711182	315	0	0
T7	11779	0	0	0
T8	26517	0	0	0
T9	489550	3574	0	0
T10	339688	5327	0	0
T12	14981	0	0	0
T14	250071	318	0	0
T15	515905	6112	0	0
T16	0	175	0	0
T25	0	2071	0	0
T26	0	1600	0	0
T27	0	276	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145334546	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145334546	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145334546	610032	0	0
T1	54506	2458	0	0
T2	22128	0	0	0
T6	711182	315	0	0
T7	11779	0	0	0
T8	26517	0	0	0
T9	489550	3574	0	0
T10	339688	5327	0	0
T12	14981	0	0	0
T14	250071	318	0	0
T15	515905	6112	0	0
T16	0	175	0	0
T25	0	2071	0	0
T26	0	1600	0	0
T27	0	276	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145334546	610032	0	0
T1	54506	2458	0	0
T2	22128	0	0	0
T6	711182	315	0	0
T7	11779	0	0	0
T8	26517	0	0	0
T9	489550	3574	0	0
T10	339688	5327	0	0
T12	14981	0	0	0
T14	250071	318	0	0
T15	515905	6112	0	0
T16	0	175	0	0
T25	0	2071	0	0
T26	0	1600	0	0
T27	0	276	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145334546	610032	0	0
T1	54506	2458	0	0
T2	22128	0	0	0
T6	711182	315	0	0
T7	11779	0	0	0
T8	26517	0	0	0
T9	489550	3574	0	0
T10	339688	5327	0	0
T12	14981	0	0	0
T14	250071	318	0	0
T15	515905	6112	0	0
T16	0	175	0	0
T25	0	2071	0	0
T26	0	1600	0	0
T27	0	276	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	145334546	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145334546	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145334546	27987302	0	0
T1	54506	53144	0	0
T2	22128	0	0	0
T6	711182	10304	0	0
T7	11779	0	0	0
T8	26517	0	0	0
T9	489550	233448	0	0
T10	339688	187160	0	0
T12	14981	0	0	0
T14	250071	26064	0	0
T15	515905	162688	0	0
T16	0	1920	0	0
T25	0	64160	0	0
T26	0	122752	0	0
T27	0	2920	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145334546	610032	0	0
T1	54506	2458	0	0
T2	22128	0	0	0
T6	711182	315	0	0
T7	11779	0	0	0
T8	26517	0	0	0
T9	489550	3574	0	0
T10	339688	5327	0	0
T12	14981	0	0	0
T14	250071	318	0	0
T15	515905	6112	0	0
T16	0	175	0	0
T25	0	2071	0	0
T26	0	1600	0	0
T27	0	276	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T9,T10

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T9,T10
1	0	Covered	T6,T9,T10

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T7
1	0	Unreachable
1	1	Covered	T6,T9,T10

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T6,T9,T10
0	0	1	Unreachable
0	0	0	Covered	T2,T6,T7

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T6,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T6,T9,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	145334546	116044760	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	145334546	760289	0	0
GntImpliesValid_A	145334546	760289	0	0
GrantKnown_A	145334546	116044760	0	0
IdxKnown_A	145334546	116044760	0	0
IndexIsCorrect_A	145334546	760289	0	0
LockArbDecision_A	145334546	0	0	0
NoReadyValidNoGrant_A	145334546	0	0	0
ReadyAndValidImplyGrant_A	145334546	760289	0	0
ReqAndReadyImplyGrant_A	145334546	760289	0	0
ReqImpliesValid_A	145334546	760289	0	0
ReqStaysHighUntilGranted0_M	145334546	0	0	0
RoundRobin_A	145334546	0	0	0
ValidKnown_A	145334546	116044760	0	0
gen_data_port_assertion.DataFlow_A	145334546	760289	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145334546	116044760	0	0
T2	22128	22128	0	0
T6	711182	696505	0	0
T7	11779	11389	0	0
T8	26517	26460	0	0
T9	489550	252719	0	0
T10	339688	147195	0	0
T12	14981	14529	0	0
T14	250071	221782	0	0
T15	515905	343611	0	0
T16	1948	0	0	0
T17	0	33552	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145334546	760289	0	0
T6	711182	11668	0	0
T7	11779	0	0	0
T8	26517	0	0	0
T9	489550	736	0	0
T10	339688	122	0	0
T12	14981	0	0	0
T14	250071	102	0	0
T15	515905	265	0	0
T16	1948	0	0	0
T17	34030	0	0	0
T25	0	540	0	0
T32	0	258	0	0
T36	0	520	0	0
T38	0	9929	0	0
T39	0	6268	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145334546	760289	0	0
T6	711182	11668	0	0
T7	11779	0	0	0
T8	26517	0	0	0
T9	489550	736	0	0
T10	339688	122	0	0
T12	14981	0	0	0
T14	250071	102	0	0
T15	515905	265	0	0
T16	1948	0	0	0
T17	34030	0	0	0
T25	0	540	0	0
T32	0	258	0	0
T36	0	520	0	0
T38	0	9929	0	0
T39	0	6268	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145334546	116044760	0	0
T2	22128	22128	0	0
T6	711182	696505	0	0
T7	11779	11389	0	0
T8	26517	26460	0	0
T9	489550	252719	0	0
T10	339688	147195	0	0
T12	14981	14529	0	0
T14	250071	221782	0	0
T15	515905	343611	0	0
T16	1948	0	0	0
T17	0	33552	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145334546	116044760	0	0
T2	22128	22128	0	0
T6	711182	696505	0	0
T7	11779	11389	0	0
T8	26517	26460	0	0
T9	489550	252719	0	0
T10	339688	147195	0	0
T12	14981	14529	0	0
T14	250071	221782	0	0
T15	515905	343611	0	0
T16	1948	0	0	0
T17	0	33552	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145334546	760289	0	0
T6	711182	11668	0	0
T7	11779	0	0	0
T8	26517	0	0	0
T9	489550	736	0	0
T10	339688	122	0	0
T12	14981	0	0	0
T14	250071	102	0	0
T15	515905	265	0	0
T16	1948	0	0	0
T17	34030	0	0	0
T25	0	540	0	0
T32	0	258	0	0
T36	0	520	0	0
T38	0	9929	0	0
T39	0	6268	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145334546	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145334546	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145334546	760289	0	0
T6	711182	11668	0	0
T7	11779	0	0	0
T8	26517	0	0	0
T9	489550	736	0	0
T10	339688	122	0	0
T12	14981	0	0	0
T14	250071	102	0	0
T15	515905	265	0	0
T16	1948	0	0	0
T17	34030	0	0	0
T25	0	540	0	0
T32	0	258	0	0
T36	0	520	0	0
T38	0	9929	0	0
T39	0	6268	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145334546	760289	0	0
T6	711182	11668	0	0
T7	11779	0	0	0
T8	26517	0	0	0
T9	489550	736	0	0
T10	339688	122	0	0
T12	14981	0	0	0
T14	250071	102	0	0
T15	515905	265	0	0
T16	1948	0	0	0
T17	34030	0	0	0
T25	0	540	0	0
T32	0	258	0	0
T36	0	520	0	0
T38	0	9929	0	0
T39	0	6268	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145334546	760289	0	0
T6	711182	11668	0	0
T7	11779	0	0	0
T8	26517	0	0	0
T9	489550	736	0	0
T10	339688	122	0	0
T12	14981	0	0	0
T14	250071	102	0	0
T15	515905	265	0	0
T16	1948	0	0	0
T17	34030	0	0	0
T25	0	540	0	0
T32	0	258	0	0
T36	0	520	0	0
T38	0	9929	0	0
T39	0	6268	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	145334546	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145334546	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145334546	116044760	0	0
T2	22128	22128	0	0
T6	711182	696505	0	0
T7	11779	11389	0	0
T8	26517	26460	0	0
T9	489550	252719	0	0
T10	339688	147195	0	0
T12	14981	14529	0	0
T14	250071	221782	0	0
T15	515905	343611	0	0
T16	1948	0	0	0
T17	0	33552	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145334546	760289	0	0
T6	711182	11668	0	0
T7	11779	0	0	0
T8	26517	0	0	0
T9	489550	736	0	0
T10	339688	122	0	0
T12	14981	0	0	0
T14	250071	102	0	0
T15	515905	265	0	0
T16	1948	0	0	0
T17	34030	0	0	0
T25	0	540	0	0
T32	0	258	0	0
T36	0	520	0	0
T38	0	9929	0	0
T39	0	6268	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T6,T9
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456230764	456146481	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	456230764	2141195	0	0
GntImpliesValid_A	456230764	2141195	0	0
GrantKnown_A	456230764	456146481	0	0
IdxKnown_A	456230764	456146481	0	0
IndexIsCorrect_A	456230764	2141195	0	0
LockArbDecision_A	456230764	0	0	0
NoReadyValidNoGrant_A	456230764	0	0	0
ReadyAndValidImplyGrant_A	456230764	2141195	0	0
ReqAndReadyImplyGrant_A	456230764	2141195	0	0
ReqImpliesValid_A	456230764	2141195	0	0
ReqStaysHighUntilGranted0_M	456230764	0	0	0
RoundRobin_A	456230764	4	0	956
ValidKnown_A	456230764	456146481	0	0
gen_data_port_assertion.DataFlow_A	456230764	2141195	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456230764	456146481	0	0
T1	381620	381548	0	0
T2	135794	135696	0	0
T3	1235	1152	0	0
T4	8897	8818	0	0
T5	2768	2674	0	0
T6	436975	436942	0	0
T7	20901	20846	0	0
T8	87390	87307	0	0
T9	172323	172233	0	0
T10	351139	351089	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456230764	2141195	0	0
T1	381620	1185	0	0
T2	135794	832	0	0
T3	1235	0	0	0
T4	8897	832	0	0
T5	2768	832	0	0
T6	436975	10178	0	0
T7	20901	832	0	0
T8	87390	832	0	0
T9	172323	4359	0	0
T10	351139	4918	0	0
T12	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456230764	2141195	0	0
T1	381620	1185	0	0
T2	135794	832	0	0
T3	1235	0	0	0
T4	8897	832	0	0
T5	2768	832	0	0
T6	436975	10178	0	0
T7	20901	832	0	0
T8	87390	832	0	0
T9	172323	4359	0	0
T10	351139	4918	0	0
T12	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456230764	456146481	0	0
T1	381620	381548	0	0
T2	135794	135696	0	0
T3	1235	1152	0	0
T4	8897	8818	0	0
T5	2768	2674	0	0
T6	436975	436942	0	0
T7	20901	20846	0	0
T8	87390	87307	0	0
T9	172323	172233	0	0
T10	351139	351089	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456230764	456146481	0	0
T1	381620	381548	0	0
T2	135794	135696	0	0
T3	1235	1152	0	0
T4	8897	8818	0	0
T5	2768	2674	0	0
T6	436975	436942	0	0
T7	20901	20846	0	0
T8	87390	87307	0	0
T9	172323	172233	0	0
T10	351139	351089	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456230764	2141195	0	0
T1	381620	1185	0	0
T2	135794	832	0	0
T3	1235	0	0	0
T4	8897	832	0	0
T5	2768	832	0	0
T6	436975	10178	0	0
T7	20901	832	0	0
T8	87390	832	0	0
T9	172323	4359	0	0
T10	351139	4918	0	0
T12	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456230764	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456230764	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456230764	2141195	0	0
T1	381620	1185	0	0
T2	135794	832	0	0
T3	1235	0	0	0
T4	8897	832	0	0
T5	2768	832	0	0
T6	436975	10178	0	0
T7	20901	832	0	0
T8	87390	832	0	0
T9	172323	4359	0	0
T10	351139	4918	0	0
T12	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456230764	2141195	0	0
T1	381620	1185	0	0
T2	135794	832	0	0
T3	1235	0	0	0
T4	8897	832	0	0
T5	2768	832	0	0
T6	436975	10178	0	0
T7	20901	832	0	0
T8	87390	832	0	0
T9	172323	4359	0	0
T10	351139	4918	0	0
T12	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456230764	2141195	0	0
T1	381620	1185	0	0
T2	135794	832	0	0
T3	1235	0	0	0
T4	8897	832	0	0
T5	2768	832	0	0
T6	436975	10178	0	0
T7	20901	832	0	0
T8	87390	832	0	0
T9	172323	4359	0	0
T10	351139	4918	0	0
T12	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456230764	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456230764	4	0	956
T23	764557	1	0	1
T24	112151	0	0	1
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	1040	0	0	1
T46	672936	0	0	1
T47	801327	0	0	1
T48	184046	0	0	1
T49	3151	0	0	1
T50	284989	0	0	1
T51	91549	0	0	1
T52	880	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456230764	456146481	0	0
T1	381620	381548	0	0
T2	135794	135696	0	0
T3	1235	1152	0	0
T4	8897	8818	0	0
T5	2768	2674	0	0
T6	436975	436942	0	0
T7	20901	20846	0	0
T8	87390	87307	0	0
T9	172323	172233	0	0
T10	351139	351089	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456230764	2141195	0	0
T1	381620	1185	0	0
T2	135794	832	0	0
T3	1235	0	0	0
T4	8897	832	0	0
T5	2768	832	0	0
T6	436975	10178	0	0
T7	20901	832	0	0
T8	87390	832	0	0
T9	172323	4359	0	0
T10	351139	4918	0	0
T12	0	832	0	0