Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3122296	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3988018

1

T1

892

T2

10858

T3

1149

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3845323	1			T1	8		T2	11186		T3	559
values[0x0]	1631650	1			T1	454		T2	5319		T3	435
values[0x1]	1633341	1			T1	436		T2	5204		T3	454

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2226525	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4883789

1

T1

894

T2

14213

T3

1215

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28412	1			T1	1		T2	96		T3	12
valid_sources[0x01]	46339	1			T1	2		T2	68		T3	10
valid_sources[0x02]	29492	1			T1	1		T2	61		T3	2
valid_sources[0x03]	30031	1			T1	7		T2	83		T3	8
valid_sources[0x04]	26372	1			T1	3		T2	72		T3	5
valid_sources[0x05]	27444	1			T1	4		T2	92		T3	6
valid_sources[0x06]	30920	1			T1	8		T2	94		T3	1
valid_sources[0x07]	26048	1			T1	3		T2	61		T3	4
valid_sources[0x08]	31386	1			T1	4		T2	75		T3	7
valid_sources[0x09]	24916	1			T1	5		T2	121		T3	2
valid_sources[0x0a]	25015	1			T1	6		T2	82		T3	6
valid_sources[0x0b]	29316	1			T1	4		T2	61		T3	7
valid_sources[0x0c]	26487	1			T1	3		T2	100		T3	2
valid_sources[0x0d]	27639	1			T1	3		T2	67		T3	7
valid_sources[0x0e]	27291	1			T1	4		T2	107		T3	8
valid_sources[0x0f]	28350	1			T2	58		T3	2		T5	60
valid_sources[0x10]	26389	1			T1	1		T2	76		T3	8
valid_sources[0x11]	29689	1			T1	7		T2	59		T3	5
valid_sources[0x12]	26783	1			T1	5		T2	69		T3	8
valid_sources[0x13]	27294	1			T1	2		T2	65		T3	5
valid_sources[0x14]	28403	1			T1	2		T2	79		T3	4
valid_sources[0x15]	26756	1			T1	3		T2	77		T3	10
valid_sources[0x16]	29532	1			T1	1		T2	74		T3	4
valid_sources[0x17]	29055	1			T1	1		T2	108		T3	4
valid_sources[0x18]	27731	1			T1	2		T2	86		T3	9
valid_sources[0x19]	25233	1			T1	2		T2	88		T3	8
valid_sources[0x1a]	25144	1			T1	2		T2	93		T3	7
valid_sources[0x1b]	25998	1			T1	6		T2	122		T3	5
valid_sources[0x1c]	27432	1			T1	4		T2	94		T3	2
valid_sources[0x1d]	29988	1			T1	4		T2	49		T3	7
valid_sources[0x1e]	25860	1			T1	4		T2	57		T3	1
valid_sources[0x1f]	34330	1			T1	1		T2	87		T3	2
valid_sources[0x20]	27696	1			T1	2		T2	105		T3	4
valid_sources[0x21]	32755	1			T1	5		T2	88		T3	4
valid_sources[0x22]	27372	1			T1	3		T2	107		T3	7
valid_sources[0x23]	29302	1			T1	7		T2	104		T3	4
valid_sources[0x24]	27781	1			T1	4		T2	79		T3	4
valid_sources[0x25]	31982	1			T1	5		T2	58		T3	3
valid_sources[0x26]	44501	1			T1	4		T2	63		T3	7
valid_sources[0x27]	25077	1			T1	2		T2	54		T3	9
valid_sources[0x28]	29096	1			T1	4		T2	110		T3	8
valid_sources[0x29]	25693	1			T1	4		T2	77		T3	5
valid_sources[0x2a]	25971	1			T1	8		T2	100		T3	7
valid_sources[0x2b]	25803	1			T1	4		T2	74		T3	3
valid_sources[0x2c]	34340	1			T1	1		T2	89		T3	6
valid_sources[0x2d]	28397	1			T1	3		T2	55		T3	6
valid_sources[0x2e]	30323	1			T1	4		T2	54		T3	1
valid_sources[0x2f]	24316	1			T1	4		T2	74		T3	4
valid_sources[0x30]	32205	1			T1	2		T2	95		T3	4
valid_sources[0x31]	28035	1			T1	2		T2	94		T3	12
valid_sources[0x32]	26159	1			T1	7		T2	99		T3	13
valid_sources[0x33]	24178	1			T1	5		T2	46		T3	5
valid_sources[0x34]	25967	1			T1	4		T2	79		T3	5
valid_sources[0x35]	24436	1			T1	3		T2	77		T3	4
valid_sources[0x36]	25134	1			T1	6		T2	90		T3	4
valid_sources[0x37]	26439	1			T1	5		T2	65		T3	4
valid_sources[0x38]	25011	1			T1	2		T2	73		T3	4
valid_sources[0x39]	24553	1			T1	6		T2	65		T3	3
valid_sources[0x3a]	28997	1			T1	1		T2	73		T3	2
valid_sources[0x3b]	29522	1			T1	1		T2	118		T3	5
valid_sources[0x3c]	25482	1			T1	3		T2	119		T3	7
valid_sources[0x3d]	25296	1			T1	1		T2	78		T3	4
valid_sources[0x3e]	24698	1			T1	1		T2	92		T3	4
valid_sources[0x3f]	28667	1			T1	1		T2	78		T3	5
valid_sources[0x40]	24918	1			T1	8		T2	102		T3	3
valid_sources[0x41]	27298	1			T1	2		T2	69		T3	7
valid_sources[0x42]	27816	1			T1	3		T2	99		T3	3
valid_sources[0x43]	25172	1			T1	2		T2	95		T3	8
valid_sources[0x44]	31410	1			T1	1		T2	93		T3	8
valid_sources[0x45]	25528	1			T1	3		T2	40		T3	9
valid_sources[0x46]	28139	1			T1	6		T2	81		T3	3
valid_sources[0x47]	26558	1			T1	3		T2	84		T3	8
valid_sources[0x48]	27287	1			T1	5		T2	70		T3	6
valid_sources[0x49]	31823	1			T1	4		T2	101		T3	1
valid_sources[0x4a]	26021	1			T1	3		T2	89		T3	4
valid_sources[0x4b]	27847	1			T1	5		T2	106		T3	7
valid_sources[0x4c]	30070	1			T1	1		T2	63		T3	11
valid_sources[0x4d]	27390	1			T1	7		T2	91		T3	11
valid_sources[0x4e]	27045	1			T1	3		T2	87		T3	7
valid_sources[0x4f]	25103	1			T1	1		T2	97		T3	9
valid_sources[0x50]	27481	1			T1	2		T2	63		T3	3
valid_sources[0x51]	25556	1			T1	5		T2	92		T3	10
valid_sources[0x52]	29514	1			T1	4		T2	120		T3	7
valid_sources[0x53]	28050	1			T1	5		T2	120		T3	4
valid_sources[0x54]	25989	1			T1	3		T2	99		T3	8
valid_sources[0x55]	28993	1			T1	2		T2	70		T3	8
valid_sources[0x56]	25640	1			T1	6		T2	83		T3	10
valid_sources[0x57]	27395	1			T1	2		T2	82		T3	4
valid_sources[0x58]	23807	1			T1	2		T2	107		T3	6
valid_sources[0x59]	24191	1			T1	6		T2	87		T3	9
valid_sources[0x5a]	29099	1			T1	4		T2	77		T3	2
valid_sources[0x5b]	29846	1			T1	4		T2	121		T3	8
valid_sources[0x5c]	27052	1			T1	5		T2	56		T3	3
valid_sources[0x5d]	28173	1			T1	2		T2	74		T3	5
valid_sources[0x5e]	24495	1			T1	6		T2	67		T3	6
valid_sources[0x5f]	30147	1			T1	2		T2	60		T3	9
valid_sources[0x60]	30779	1			T1	4		T2	62		T3	12
valid_sources[0x61]	31873	1			T1	4		T2	78		T3	4
valid_sources[0x62]	30899	1			T1	4		T2	88		T3	12
valid_sources[0x63]	28863	1			T1	7		T2	75		T3	3
valid_sources[0x64]	26697	1			T1	2		T2	72		T3	11
valid_sources[0x65]	25357	1			T1	9		T2	87		T3	6
valid_sources[0x66]	24484	1			T1	6		T2	146		T3	4
valid_sources[0x67]	25451	1			T1	6		T2	87		T3	6
valid_sources[0x68]	54870	1			T1	6		T2	122		T3	2
valid_sources[0x69]	26465	1			T2	80		T3	7		T5	17
valid_sources[0x6a]	25358	1			T1	3		T2	78		T3	5
valid_sources[0x6b]	26183	1			T1	3		T2	91		T3	4
valid_sources[0x6c]	26415	1			T1	6		T2	107		T3	6
valid_sources[0x6d]	28342	1			T1	1		T2	92		T3	6
valid_sources[0x6e]	26010	1			T1	1		T2	75		T3	10
valid_sources[0x6f]	27295	1			T1	5		T2	109		T3	4
valid_sources[0x70]	25446	1			T1	2		T2	64		T3	4
valid_sources[0x71]	24349	1			T1	5		T2	89		T3	4
valid_sources[0x72]	25298	1			T1	3		T2	70		T3	7
valid_sources[0x73]	26029	1			T1	6		T2	99		T3	9
valid_sources[0x74]	33874	1			T1	1		T2	104		T3	7
valid_sources[0x75]	26874	1			T1	1		T2	93		T3	7
valid_sources[0x76]	27155	1			T1	6		T2	76		T3	7
valid_sources[0x77]	25496	1			T1	7		T2	81		T3	7
valid_sources[0x78]	42447	1			T1	5		T2	81		T3	2
valid_sources[0x79]	28859	1			T1	3		T2	72		T3	1
valid_sources[0x7a]	26079	1			T1	2		T2	107		T3	9
valid_sources[0x7b]	29754	1			T1	7		T2	73		T3	2
valid_sources[0x7c]	27080	1			T1	3		T2	97		T3	4
valid_sources[0x7d]	25278	1			T1	2		T2	115		T3	8
valid_sources[0x7e]	24102	1			T1	2		T2	82		T3	1
valid_sources[0x7f]	29343	1			T1	4		T2	79		T3	2
valid_sources[0x80]	25596	1			T1	4		T2	112		T3	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1009072

1

T1

5

T2

1438

T3

273

values[0x0]

all_enables

biggest_size

1500239

1

T1

453

T2

4775

T3

430

values[0x1]

all_enables

biggest_size

1478707

1

T1

434

T2

4645

T3

446