Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3140975

1

T1

6

T2

10851

T3

299

full_word

3989089

1

T1

892

T2

10858

T3

1149

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7129704	1			T1	898		T2	21709		T3	1448
auto[TlIntgErrCmd]	129	1			T64	2		T66	3		T93	12
auto[TlIntgErrData]	136	1			T64	4		T66	3		T93	11
auto[TlIntgErrBoth]	95	1			T64	4		T66	4		T93	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3848582

1

T1

8

T2

11186

T3

559

auto[1]

3281482

1

T1

890

T2

10523

T3

889

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	2839096	1			T1	3		T2	9748		T3	286
auto[TlIntgErrNone]	partial	auto[1]	301555	1			T1	3		T2	1103		T3	13
auto[TlIntgErrNone]	full_word	auto[0]	1009319	1			T1	5		T2	1438		T3	273
auto[TlIntgErrNone]	full_word	auto[1]	2979734	1			T1	887		T2	9420		T3	876
auto[TlIntgErrCmd]	partial	auto[0]	63	1			T66	1		T93	9		T144	2
auto[TlIntgErrCmd]	partial	auto[1]	59	1			T64	2		T66	2		T93	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T165	1		T160	1		T166	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T107	1		T167	2		T166	1
auto[TlIntgErrData]	partial	auto[0]	51	1			T64	1		T93	4		T144	2
auto[TlIntgErrData]	partial	auto[1]	63	1			T64	3		T66	3		T93	6
auto[TlIntgErrData]	full_word	auto[0]	12	1			T93	1		T107	1		T144	2
auto[TlIntgErrData]	full_word	auto[1]	10	1			T144	1		T162	1		T168	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T64	3		T66	3		T93	4
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T64	1		T66	1		T93	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T168	1		T164	1		T161	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T93	1		T144	1		T168	1