Unified Coverage Report :: Module :: prim_generic_ram_1r1w

Module : prim_generic_ram_1r1w

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1r1w

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	555542936	3187694	0	0
gen_wmask[1].MaskCheckPortA_A	555542936	3187694	0	0
gen_wmask[2].MaskCheckPortA_A	555542936	3187694	0	0
gen_wmask[3].MaskCheckPortA_A	555542936	3187694	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555542936	3187694	0	0
T1	76906	832	0	0
T2	417146	8531	0	0
T3	37922	832	0	0
T4	1403	0	0	0
T5	278580	832	0	0
T6	5175	16	0	0
T7	315614	832	0	0
T8	3439	832	0	0
T9	574454	7085	0	0
T10	854896	7706	0	0
T11	2640	73	0	0
T12	29543	0	0	0
T13	17326	0	0	0
T16	0	19384	0	0
T25	0	10300	0	0
T27	0	283	0	0
T28	0	1028	0	0
T41	0	1991	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555542936	3187694	0	0
T1	76906	832	0	0
T2	417146	8531	0	0
T3	37922	832	0	0
T4	1403	0	0	0
T5	278580	832	0	0
T6	5175	16	0	0
T7	315614	832	0	0
T8	3439	832	0	0
T9	574454	7085	0	0
T10	854896	7706	0	0
T11	2640	73	0	0
T12	29543	0	0	0
T13	17326	0	0	0
T16	0	19384	0	0
T25	0	10300	0	0
T27	0	283	0	0
T28	0	1028	0	0
T41	0	1991	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555542936	3187694	0	0
T1	76906	832	0	0
T2	417146	8531	0	0
T3	37922	832	0	0
T4	1403	0	0	0
T5	278580	832	0	0
T6	5175	16	0	0
T7	315614	832	0	0
T8	3439	832	0	0
T9	574454	7085	0	0
T10	854896	7706	0	0
T11	2640	73	0	0
T12	29543	0	0	0
T13	17326	0	0	0
T16	0	19384	0	0
T25	0	10300	0	0
T27	0	283	0	0
T28	0	1028	0	0
T41	0	1991	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	555542936	3187694	0	0
T1	76906	832	0	0
T2	417146	8531	0	0
T3	37922	832	0	0
T4	1403	0	0	0
T5	278580	832	0	0
T6	5175	16	0	0
T7	315614	832	0	0
T8	3439	832	0	0
T9	574454	7085	0	0
T10	854896	7706	0	0
T11	2640	73	0	0
T12	29543	0	0	0
T13	17326	0	0	0
T16	0	19384	0	0
T25	0	10300	0	0
T27	0	283	0	0
T28	0	1028	0	0
T41	0	1991	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			==> MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	414560164	2034954	0	0
gen_wmask[1].MaskCheckPortA_A	414560164	2034954	0	0
gen_wmask[2].MaskCheckPortA_A	414560164	2034954	0	0
gen_wmask[3].MaskCheckPortA_A	414560164	2034954	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414560164	2034954	0	0
T1	76906	832	0	0
T2	120478	5339	0	0
T3	15104	832	0	0
T4	1403	0	0	0
T5	186784	832	0	0
T6	4743	2	0	0
T7	270958	832	0	0
T8	3439	832	0	0
T9	175321	4992	0	0
T10	287841	4992	0	0
T11	0	64	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414560164	2034954	0	0
T1	76906	832	0	0
T2	120478	5339	0	0
T3	15104	832	0	0
T4	1403	0	0	0
T5	186784	832	0	0
T6	4743	2	0	0
T7	270958	832	0	0
T8	3439	832	0	0
T9	175321	4992	0	0
T10	287841	4992	0	0
T11	0	64	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414560164	2034954	0	0
T1	76906	832	0	0
T2	120478	5339	0	0
T3	15104	832	0	0
T4	1403	0	0	0
T5	186784	832	0	0
T6	4743	2	0	0
T7	270958	832	0	0
T8	3439	832	0	0
T9	175321	4992	0	0
T10	287841	4992	0	0
T11	0	64	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414560164	2034954	0	0
T1	76906	832	0	0
T2	120478	5339	0	0
T3	15104	832	0	0
T4	1403	0	0	0
T5	186784	832	0	0
T6	4743	2	0	0
T7	270958	832	0	0
T8	3439	832	0	0
T9	175321	4992	0	0
T10	287841	4992	0	0
T11	0	64	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	140982772	1152740	0	0
gen_wmask[1].MaskCheckPortA_A	140982772	1152740	0	0
gen_wmask[2].MaskCheckPortA_A	140982772	1152740	0	0
gen_wmask[3].MaskCheckPortA_A	140982772	1152740	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140982772	1152740	0	0
T2	296668	3192	0	0
T3	22818	0	0	0
T5	91796	0	0	0
T6	432	14	0	0
T7	44656	0	0	0
T9	399133	2093	0	0
T10	567055	2714	0	0
T11	2640	9	0	0
T12	29543	0	0	0
T13	17326	0	0	0
T16	0	19384	0	0
T25	0	10300	0	0
T27	0	283	0	0
T28	0	1028	0	0
T41	0	1991	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140982772	1152740	0	0
T2	296668	3192	0	0
T3	22818	0	0	0
T5	91796	0	0	0
T6	432	14	0	0
T7	44656	0	0	0
T9	399133	2093	0	0
T10	567055	2714	0	0
T11	2640	9	0	0
T12	29543	0	0	0
T13	17326	0	0	0
T16	0	19384	0	0
T25	0	10300	0	0
T27	0	283	0	0
T28	0	1028	0	0
T41	0	1991	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140982772	1152740	0	0
T2	296668	3192	0	0
T3	22818	0	0	0
T5	91796	0	0	0
T6	432	14	0	0
T7	44656	0	0	0
T9	399133	2093	0	0
T10	567055	2714	0	0
T11	2640	9	0	0
T12	29543	0	0	0
T13	17326	0	0	0
T16	0	19384	0	0
T25	0	10300	0	0
T27	0	283	0	0
T28	0	1028	0	0
T41	0	1991	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140982772	1152740	0	0
T2	296668	3192	0	0
T3	22818	0	0	0
T5	91796	0	0	0
T6	432	14	0	0
T7	44656	0	0	0
T9	399133	2093	0	0
T10	567055	2714	0	0
T11	2640	9	0	0
T12	29543	0	0	0
T13	17326	0	0	0
T16	0	19384	0	0
T25	0	10300	0	0
T27	0	283	0	0
T28	0	1028	0	0
T41	0	1991	0	0