Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	416860535	2825097	0	0
DepthKnown_A	416860535	416730806	0	0
RvalidKnown_A	416860535	416730806	0	0
WreadyKnown_A	416860535	416730806	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416860535	2825097	0	0
T1	76906	832	0	0
T2	120478	7485	0	0
T3	15104	1663	0	0
T4	1403	0	0	0
T5	186784	1663	0	0
T6	4743	0	0	0
T7	270958	1663	0	0
T8	3439	1667	0	0
T9	175321	8337	0	0
T10	287841	7492	0	0
T12	0	2174	0	0
T13	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416860535	416730806	0	0
T1	76906	76814	0	0
T2	120478	120472	0	0
T3	15104	15042	0	0
T4	1403	1343	0	0
T5	186784	186706	0	0
T6	4743	4677	0	0
T7	270958	270875	0	0
T8	3439	3367	0	0
T9	175321	175248	0	0
T10	287841	287836	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416860535	416730806	0	0
T1	76906	76814	0	0
T2	120478	120472	0	0
T3	15104	15042	0	0
T4	1403	1343	0	0
T5	186784	186706	0	0
T6	4743	4677	0	0
T7	270958	270875	0	0
T8	3439	3367	0	0
T9	175321	175248	0	0
T10	287841	287836	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416860535	416730806	0	0
T1	76906	76814	0	0
T2	120478	120472	0	0
T3	15104	15042	0	0
T4	1403	1343	0	0
T5	186784	186706	0	0
T6	4743	4677	0	0
T7	270958	270875	0	0
T8	3439	3367	0	0
T9	175321	175248	0	0
T10	287841	287836	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	416860535	2912763	0	0
DepthKnown_A	416860535	416730806	0	0
RvalidKnown_A	416860535	416730806	0	0
WreadyKnown_A	416860535	416730806	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416860535	2912763	0	0
T1	76906	3728	0	0
T2	120478	4992	0	0
T3	15104	832	0	0
T4	1403	0	0	0
T5	186784	832	0	0
T6	4743	0	0	0
T7	270958	832	0	0
T8	3439	836	0	0
T9	175321	10881	0	0
T10	287841	10093	0	0
T12	0	1088	0	0
T13	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416860535	416730806	0	0
T1	76906	76814	0	0
T2	120478	120472	0	0
T3	15104	15042	0	0
T4	1403	1343	0	0
T5	186784	186706	0	0
T6	4743	4677	0	0
T7	270958	270875	0	0
T8	3439	3367	0	0
T9	175321	175248	0	0
T10	287841	287836	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416860535	416730806	0	0
T1	76906	76814	0	0
T2	120478	120472	0	0
T3	15104	15042	0	0
T4	1403	1343	0	0
T5	186784	186706	0	0
T6	4743	4677	0	0
T7	270958	270875	0	0
T8	3439	3367	0	0
T9	175321	175248	0	0
T10	287841	287836	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416860535	416730806	0	0
T1	76906	76814	0	0
T2	120478	120472	0	0
T3	15104	15042	0	0
T4	1403	1343	0	0
T5	186784	186706	0	0
T6	4743	4677	0	0
T7	270958	270875	0	0
T8	3439	3367	0	0
T9	175321	175248	0	0
T10	287841	287836	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	416860535	176573	0	0
DepthKnown_A	416860535	416730806	0	0
RvalidKnown_A	416860535	416730806	0	0
WreadyKnown_A	416860535	416730806	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416860535	176573	0	0
T2	120478	473	0	0
T3	15104	0	0	0
T4	1403	0	0	0
T5	186784	0	0	0
T6	4743	4	0	0
T7	270958	0	0	0
T8	3439	0	0	0
T9	175321	128	0	0
T10	287841	251	0	0
T11	22067	3	0	0
T16	0	2581	0	0
T25	0	1465	0	0
T27	0	66	0	0
T28	0	128	0	0
T41	0	128	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416860535	416730806	0	0
T1	76906	76814	0	0
T2	120478	120472	0	0
T3	15104	15042	0	0
T4	1403	1343	0	0
T5	186784	186706	0	0
T6	4743	4677	0	0
T7	270958	270875	0	0
T8	3439	3367	0	0
T9	175321	175248	0	0
T10	287841	287836	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416860535	416730806	0	0
T1	76906	76814	0	0
T2	120478	120472	0	0
T3	15104	15042	0	0
T4	1403	1343	0	0
T5	186784	186706	0	0
T6	4743	4677	0	0
T7	270958	270875	0	0
T8	3439	3367	0	0
T9	175321	175248	0	0
T10	287841	287836	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416860535	416730806	0	0
T1	76906	76814	0	0
T2	120478	120472	0	0
T3	15104	15042	0	0
T4	1403	1343	0	0
T5	186784	186706	0	0
T6	4743	4677	0	0
T7	270958	270875	0	0
T8	3439	3367	0	0
T9	175321	175248	0	0
T10	287841	287836	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	416860535	359336	0	0
DepthKnown_A	416860535	416730806	0	0
RvalidKnown_A	416860535	416730806	0	0
WreadyKnown_A	416860535	416730806	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416860535	359336	0	0
T2	120478	473	0	0
T3	15104	0	0	0
T4	1403	0	0	0
T5	186784	0	0	0
T6	4743	4	0	0
T7	270958	0	0	0
T8	3439	0	0	0
T9	175321	587	0	0
T10	287841	722	0	0
T11	22067	11	0	0
T16	0	2581	0	0
T25	0	6621	0	0
T27	0	66	0	0
T28	0	128	0	0
T41	0	128	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416860535	416730806	0	0
T1	76906	76814	0	0
T2	120478	120472	0	0
T3	15104	15042	0	0
T4	1403	1343	0	0
T5	186784	186706	0	0
T6	4743	4677	0	0
T7	270958	270875	0	0
T8	3439	3367	0	0
T9	175321	175248	0	0
T10	287841	287836	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416860535	416730806	0	0
T1	76906	76814	0	0
T2	120478	120472	0	0
T3	15104	15042	0	0
T4	1403	1343	0	0
T5	186784	186706	0	0
T6	4743	4677	0	0
T7	270958	270875	0	0
T8	3439	3367	0	0
T9	175321	175248	0	0
T10	287841	287836	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416860535	416730806	0	0
T1	76906	76814	0	0
T2	120478	120472	0	0
T3	15104	15042	0	0
T4	1403	1343	0	0
T5	186784	186706	0	0
T6	4743	4677	0	0
T7	270958	270875	0	0
T8	3439	3367	0	0
T9	175321	175248	0	0
T10	287841	287836	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	416860535	5428402	0	0
DepthKnown_A	416860535	416730806	0	0
RvalidKnown_A	416860535	416730806	0	0
WreadyKnown_A	416860535	416730806	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416860535	5428402	0	0
T1	76906	66	0	0
T2	120478	16344	0	0
T3	15104	616	0	0
T4	1403	8	0	0
T5	186784	7948	0	0
T6	4743	401	0	0
T7	270958	47	0	0
T8	3439	45	0	0
T9	175321	659	0	0
T10	287841	4398	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416860535	416730806	0	0
T1	76906	76814	0	0
T2	120478	120472	0	0
T3	15104	15042	0	0
T4	1403	1343	0	0
T5	186784	186706	0	0
T6	4743	4677	0	0
T7	270958	270875	0	0
T8	3439	3367	0	0
T9	175321	175248	0	0
T10	287841	287836	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416860535	416730806	0	0
T1	76906	76814	0	0
T2	120478	120472	0	0
T3	15104	15042	0	0
T4	1403	1343	0	0
T5	186784	186706	0	0
T6	4743	4677	0	0
T7	270958	270875	0	0
T8	3439	3367	0	0
T9	175321	175248	0	0
T10	287841	287836	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416860535	416730806	0	0
T1	76906	76814	0	0
T2	120478	120472	0	0
T3	15104	15042	0	0
T4	1403	1343	0	0
T5	186784	186706	0	0
T6	4743	4677	0	0
T7	270958	270875	0	0
T8	3439	3367	0	0
T9	175321	175248	0	0
T10	287841	287836	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	416860535	10045761	0	0
DepthKnown_A	416860535	416730806	0	0
RvalidKnown_A	416860535	416730806	0	0
WreadyKnown_A	416860535	416730806	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416860535	10045761	0	0
T1	76906	280	0	0
T2	120478	16244	0	0
T3	15104	616	0	0
T4	1403	8	0	0
T5	186784	24169	0	0
T6	4743	401	0	0
T7	270958	152	0	0
T8	3439	183	0	0
T9	175321	2758	0	0
T10	287841	13905	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416860535	416730806	0	0
T1	76906	76814	0	0
T2	120478	120472	0	0
T3	15104	15042	0	0
T4	1403	1343	0	0
T5	186784	186706	0	0
T6	4743	4677	0	0
T7	270958	270875	0	0
T8	3439	3367	0	0
T9	175321	175248	0	0
T10	287841	287836	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416860535	416730806	0	0
T1	76906	76814	0	0
T2	120478	120472	0	0
T3	15104	15042	0	0
T4	1403	1343	0	0
T5	186784	186706	0	0
T6	4743	4677	0	0
T7	270958	270875	0	0
T8	3439	3367	0	0
T9	175321	175248	0	0
T10	287841	287836	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416860535	416730806	0	0
T1	76906	76814	0	0
T2	120478	120472	0	0
T3	15104	15042	0	0
T4	1403	1343	0	0
T5	186784	186706	0	0
T6	4743	4677	0	0
T7	270958	270875	0	0
T8	3439	3367	0	0
T9	175321	175248	0	0
T10	287841	287836	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0