Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T6,T11
1	0	Covered	T2,T6,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T11
1	0	Unreachable
1	1	Covered	T2,T6,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T9,T10

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T9,T10
1	0	Covered	T2,T9,T10

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T9,T10

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T6,T9
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	696525708	554176437	0	0
CheckNGreaterZero_A	2868	2868	0	0
GntImpliesReady_A	696525708	3551868	0	0
GntImpliesValid_A	696525708	3551868	0	0
GrantKnown_A	696525708	554176437	0	0
IdxKnown_A	696525708	554176437	0	0
IndexIsCorrect_A	696525708	3551868	0	0
LockArbDecision_A	696525708	0	0	0
NoReadyValidNoGrant_A	696525708	0	0	0
ReadyAndValidImplyGrant_A	696525708	3551868	0	0
ReqAndReadyImplyGrant_A	696525708	3551868	0	0
ReqImpliesValid_A	696525708	3551868	0	0
ReqStaysHighUntilGranted0_M	696525708	0	0	0
RoundRobin_A	696525708	6	0	956
ValidKnown_A	696525708	554176437	0	0
gen_data_port_assertion.DataFlow_A	696525708	3551868	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696525708	554176437	0	0
T1	98986	98894	0	0
T2	713814	414470	0	0
T3	60740	37860	0	0
T4	1403	1343	0	0
T5	370376	278502	0	0
T6	5607	5109	0	0
T7	360270	315531	0	0
T8	3439	3367	0	0
T9	973587	572806	0	0
T10	1421951	852142	0	0
T11	5280	2640	0	0
T12	59086	29543	0	0
T13	17326	17098	0	0
T14	0	6153	0	0
T16	0	281728	0	0
T25	0	216136	0	0
T30	0	90376	0	0
T31	0	864	0	0
T32	0	288	0	0
T33	0	87776	0	0
T34	0	51680	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2868	2868	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696525708	3551868	0	0
T1	76906	832	0	0
T2	713814	9392	0	0
T3	60740	832	0	0
T4	1403	0	0	0
T5	370376	832	0	0
T6	5607	24	0	0
T7	360270	832	0	0
T8	3439	832	0	0
T9	973587	7216	0	0
T10	1421951	7970	0	0
T11	5280	145	0	0
T12	59086	0	0	0
T13	34652	0	0	0
T16	0	23001	0	0
T17	0	442	0	0
T18	0	5736	0	0
T25	0	11961	0	0
T27	0	283	0	0
T28	0	1028	0	0
T33	0	3968	0	0
T41	0	1991	0	0
T44	0	3653	0	0
T46	0	554	0	0
T47	0	3518	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696525708	3551868	0	0
T1	76906	832	0	0
T2	713814	9392	0	0
T3	60740	832	0	0
T4	1403	0	0	0
T5	370376	832	0	0
T6	5607	24	0	0
T7	360270	832	0	0
T8	3439	832	0	0
T9	973587	7216	0	0
T10	1421951	7970	0	0
T11	5280	145	0	0
T12	59086	0	0	0
T13	34652	0	0	0
T16	0	23001	0	0
T17	0	442	0	0
T18	0	5736	0	0
T25	0	11961	0	0
T27	0	283	0	0
T28	0	1028	0	0
T33	0	3968	0	0
T41	0	1991	0	0
T44	0	3653	0	0
T46	0	554	0	0
T47	0	3518	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696525708	554176437	0	0
T1	98986	98894	0	0
T2	713814	414470	0	0
T3	60740	37860	0	0
T4	1403	1343	0	0
T5	370376	278502	0	0
T6	5607	5109	0	0
T7	360270	315531	0	0
T8	3439	3367	0	0
T9	973587	572806	0	0
T10	1421951	852142	0	0
T11	5280	2640	0	0
T12	59086	29543	0	0
T13	17326	17098	0	0
T14	0	6153	0	0
T16	0	281728	0	0
T25	0	216136	0	0
T30	0	90376	0	0
T31	0	864	0	0
T32	0	288	0	0
T33	0	87776	0	0
T34	0	51680	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696525708	554176437	0	0
T1	98986	98894	0	0
T2	713814	414470	0	0
T3	60740	37860	0	0
T4	1403	1343	0	0
T5	370376	278502	0	0
T6	5607	5109	0	0
T7	360270	315531	0	0
T8	3439	3367	0	0
T9	973587	572806	0	0
T10	1421951	852142	0	0
T11	5280	2640	0	0
T12	59086	29543	0	0
T13	17326	17098	0	0
T14	0	6153	0	0
T16	0	281728	0	0
T25	0	216136	0	0
T30	0	90376	0	0
T31	0	864	0	0
T32	0	288	0	0
T33	0	87776	0	0
T34	0	51680	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696525708	3551868	0	0
T1	76906	832	0	0
T2	713814	9392	0	0
T3	60740	832	0	0
T4	1403	0	0	0
T5	370376	832	0	0
T6	5607	24	0	0
T7	360270	832	0	0
T8	3439	832	0	0
T9	973587	7216	0	0
T10	1421951	7970	0	0
T11	5280	145	0	0
T12	59086	0	0	0
T13	34652	0	0	0
T16	0	23001	0	0
T17	0	442	0	0
T18	0	5736	0	0
T25	0	11961	0	0
T27	0	283	0	0
T28	0	1028	0	0
T33	0	3968	0	0
T41	0	1991	0	0
T44	0	3653	0	0
T46	0	554	0	0
T47	0	3518	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696525708	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696525708	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696525708	3551868	0	0
T1	76906	832	0	0
T2	713814	9392	0	0
T3	60740	832	0	0
T4	1403	0	0	0
T5	370376	832	0	0
T6	5607	24	0	0
T7	360270	832	0	0
T8	3439	832	0	0
T9	973587	7216	0	0
T10	1421951	7970	0	0
T11	5280	145	0	0
T12	59086	0	0	0
T13	34652	0	0	0
T16	0	23001	0	0
T17	0	442	0	0
T18	0	5736	0	0
T25	0	11961	0	0
T27	0	283	0	0
T28	0	1028	0	0
T33	0	3968	0	0
T41	0	1991	0	0
T44	0	3653	0	0
T46	0	554	0	0
T47	0	3518	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696525708	3551868	0	0
T1	76906	832	0	0
T2	713814	9392	0	0
T3	60740	832	0	0
T4	1403	0	0	0
T5	370376	832	0	0
T6	5607	24	0	0
T7	360270	832	0	0
T8	3439	832	0	0
T9	973587	7216	0	0
T10	1421951	7970	0	0
T11	5280	145	0	0
T12	59086	0	0	0
T13	34652	0	0	0
T16	0	23001	0	0
T17	0	442	0	0
T18	0	5736	0	0
T25	0	11961	0	0
T27	0	283	0	0
T28	0	1028	0	0
T33	0	3968	0	0
T41	0	1991	0	0
T44	0	3653	0	0
T46	0	554	0	0
T47	0	3518	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696525708	3551868	0	0
T1	76906	832	0	0
T2	713814	9392	0	0
T3	60740	832	0	0
T4	1403	0	0	0
T5	370376	832	0	0
T6	5607	24	0	0
T7	360270	832	0	0
T8	3439	832	0	0
T9	973587	7216	0	0
T10	1421951	7970	0	0
T11	5280	145	0	0
T12	59086	0	0	0
T13	34652	0	0	0
T16	0	23001	0	0
T17	0	442	0	0
T18	0	5736	0	0
T25	0	11961	0	0
T27	0	283	0	0
T28	0	1028	0	0
T33	0	3968	0	0
T41	0	1991	0	0
T44	0	3653	0	0
T46	0	554	0	0
T47	0	3518	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	696525708	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696525708	6	0	956
T48	188249	2	0	1
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	4054	0	0	1
T54	59466	0	0	1
T55	314323	0	0	1
T56	128234	0	0	1
T57	63113	0	0	1
T58	1368	0	0	1
T59	260257	0	0	1
T60	13104	0	0	1
T61	97850	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696525708	554176437	0	0
T1	98986	98894	0	0
T2	713814	414470	0	0
T3	60740	37860	0	0
T4	1403	1343	0	0
T5	370376	278502	0	0
T6	5607	5109	0	0
T7	360270	315531	0	0
T8	3439	3367	0	0
T9	973587	572806	0	0
T10	1421951	852142	0	0
T11	5280	2640	0	0
T12	59086	29543	0	0
T13	17326	17098	0	0
T14	0	6153	0	0
T16	0	281728	0	0
T25	0	216136	0	0
T30	0	90376	0	0
T31	0	864	0	0
T32	0	288	0	0
T33	0	87776	0	0
T34	0	51680	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696525708	3551868	0	0
T1	76906	832	0	0
T2	713814	9392	0	0
T3	60740	832	0	0
T4	1403	0	0	0
T5	370376	832	0	0
T6	5607	24	0	0
T7	360270	832	0	0
T8	3439	832	0	0
T9	973587	7216	0	0
T10	1421951	7970	0	0
T11	5280	145	0	0
T12	59086	0	0	0
T13	34652	0	0	0
T16	0	23001	0	0
T17	0	442	0	0
T18	0	5736	0	0
T25	0	11961	0	0
T27	0	283	0	0
T28	0	1028	0	0
T33	0	3968	0	0
T41	0	1991	0	0
T44	0	3653	0	0
T46	0	554	0	0
T47	0	3518	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T6,T11
1	0	Covered	T2,T6,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T11
1	0	Unreachable
1	1	Covered	T2,T6,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T6,T11
0	0	1	Unreachable
0	0	0	Covered	T2,T6,T11

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	140982772	26202878	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	140982772	595148	0	0
GntImpliesValid_A	140982772	595148	0	0
GrantKnown_A	140982772	26202878	0	0
IdxKnown_A	140982772	26202878	0	0
IndexIsCorrect_A	140982772	595148	0	0
LockArbDecision_A	140982772	0	0	0
NoReadyValidNoGrant_A	140982772	0	0	0
ReadyAndValidImplyGrant_A	140982772	595148	0	0
ReqAndReadyImplyGrant_A	140982772	595148	0	0
ReqImpliesValid_A	140982772	595148	0	0
ReqStaysHighUntilGranted0_M	140982772	0	0	0
RoundRobin_A	140982772	0	0	0
ValidKnown_A	140982772	26202878	0	0
gen_data_port_assertion.DataFlow_A	140982772	595148	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140982772	26202878	0	0
T2	296668	28888	0	0
T3	22818	0	0	0
T5	91796	0	0	0
T6	432	432	0	0
T7	44656	0	0	0
T9	399133	0	0	0
T10	567055	0	0	0
T11	2640	2640	0	0
T12	29543	0	0	0
T13	17326	0	0	0
T16	0	281728	0	0
T25	0	216136	0	0
T30	0	90376	0	0
T31	0	864	0	0
T32	0	288	0	0
T33	0	87776	0	0
T34	0	51680	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140982772	595148	0	0
T2	296668	1331	0	0
T3	22818	0	0	0
T5	91796	0	0	0
T6	432	18	0	0
T7	44656	0	0	0
T9	399133	0	0	0
T10	567055	0	0	0
T11	2640	78	0	0
T12	29543	0	0	0
T13	17326	0	0	0
T16	0	11586	0	0
T17	0	442	0	0
T18	0	5736	0	0
T25	0	5191	0	0
T33	0	3711	0	0
T44	0	3653	0	0
T46	0	554	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140982772	595148	0	0
T2	296668	1331	0	0
T3	22818	0	0	0
T5	91796	0	0	0
T6	432	18	0	0
T7	44656	0	0	0
T9	399133	0	0	0
T10	567055	0	0	0
T11	2640	78	0	0
T12	29543	0	0	0
T13	17326	0	0	0
T16	0	11586	0	0
T17	0	442	0	0
T18	0	5736	0	0
T25	0	5191	0	0
T33	0	3711	0	0
T44	0	3653	0	0
T46	0	554	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140982772	26202878	0	0
T2	296668	28888	0	0
T3	22818	0	0	0
T5	91796	0	0	0
T6	432	432	0	0
T7	44656	0	0	0
T9	399133	0	0	0
T10	567055	0	0	0
T11	2640	2640	0	0
T12	29543	0	0	0
T13	17326	0	0	0
T16	0	281728	0	0
T25	0	216136	0	0
T30	0	90376	0	0
T31	0	864	0	0
T32	0	288	0	0
T33	0	87776	0	0
T34	0	51680	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140982772	26202878	0	0
T2	296668	28888	0	0
T3	22818	0	0	0
T5	91796	0	0	0
T6	432	432	0	0
T7	44656	0	0	0
T9	399133	0	0	0
T10	567055	0	0	0
T11	2640	2640	0	0
T12	29543	0	0	0
T13	17326	0	0	0
T16	0	281728	0	0
T25	0	216136	0	0
T30	0	90376	0	0
T31	0	864	0	0
T32	0	288	0	0
T33	0	87776	0	0
T34	0	51680	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140982772	595148	0	0
T2	296668	1331	0	0
T3	22818	0	0	0
T5	91796	0	0	0
T6	432	18	0	0
T7	44656	0	0	0
T9	399133	0	0	0
T10	567055	0	0	0
T11	2640	78	0	0
T12	29543	0	0	0
T13	17326	0	0	0
T16	0	11586	0	0
T17	0	442	0	0
T18	0	5736	0	0
T25	0	5191	0	0
T33	0	3711	0	0
T44	0	3653	0	0
T46	0	554	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140982772	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140982772	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140982772	595148	0	0
T2	296668	1331	0	0
T3	22818	0	0	0
T5	91796	0	0	0
T6	432	18	0	0
T7	44656	0	0	0
T9	399133	0	0	0
T10	567055	0	0	0
T11	2640	78	0	0
T12	29543	0	0	0
T13	17326	0	0	0
T16	0	11586	0	0
T17	0	442	0	0
T18	0	5736	0	0
T25	0	5191	0	0
T33	0	3711	0	0
T44	0	3653	0	0
T46	0	554	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140982772	595148	0	0
T2	296668	1331	0	0
T3	22818	0	0	0
T5	91796	0	0	0
T6	432	18	0	0
T7	44656	0	0	0
T9	399133	0	0	0
T10	567055	0	0	0
T11	2640	78	0	0
T12	29543	0	0	0
T13	17326	0	0	0
T16	0	11586	0	0
T17	0	442	0	0
T18	0	5736	0	0
T25	0	5191	0	0
T33	0	3711	0	0
T44	0	3653	0	0
T46	0	554	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140982772	595148	0	0
T2	296668	1331	0	0
T3	22818	0	0	0
T5	91796	0	0	0
T6	432	18	0	0
T7	44656	0	0	0
T9	399133	0	0	0
T10	567055	0	0	0
T11	2640	78	0	0
T12	29543	0	0	0
T13	17326	0	0	0
T16	0	11586	0	0
T17	0	442	0	0
T18	0	5736	0	0
T25	0	5191	0	0
T33	0	3711	0	0
T44	0	3653	0	0
T46	0	554	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	140982772	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140982772	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140982772	26202878	0	0
T2	296668	28888	0	0
T3	22818	0	0	0
T5	91796	0	0	0
T6	432	432	0	0
T7	44656	0	0	0
T9	399133	0	0	0
T10	567055	0	0	0
T11	2640	2640	0	0
T12	29543	0	0	0
T13	17326	0	0	0
T16	0	281728	0	0
T25	0	216136	0	0
T30	0	90376	0	0
T31	0	864	0	0
T32	0	288	0	0
T33	0	87776	0	0
T34	0	51680	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140982772	595148	0	0
T2	296668	1331	0	0
T3	22818	0	0	0
T5	91796	0	0	0
T6	432	18	0	0
T7	44656	0	0	0
T9	399133	0	0	0
T10	567055	0	0	0
T11	2640	78	0	0
T12	29543	0	0	0
T13	17326	0	0	0
T16	0	11586	0	0
T17	0	442	0	0
T18	0	5736	0	0
T25	0	5191	0	0
T33	0	3711	0	0
T44	0	3653	0	0
T46	0	554	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T9,T10

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T9,T10
1	0	Covered	T2,T9,T10

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T9,T10

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T9,T10
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	140982772	113500253	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	140982772	752239	0	0
GntImpliesValid_A	140982772	752239	0	0
GrantKnown_A	140982772	113500253	0	0
IdxKnown_A	140982772	113500253	0	0
IndexIsCorrect_A	140982772	752239	0	0
LockArbDecision_A	140982772	0	0	0
NoReadyValidNoGrant_A	140982772	0	0	0
ReadyAndValidImplyGrant_A	140982772	752239	0	0
ReqAndReadyImplyGrant_A	140982772	752239	0	0
ReqImpliesValid_A	140982772	752239	0	0
ReqStaysHighUntilGranted0_M	140982772	0	0	0
RoundRobin_A	140982772	0	0	0
ValidKnown_A	140982772	113500253	0	0
gen_data_port_assertion.DataFlow_A	140982772	752239	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140982772	113500253	0	0
T1	22080	22080	0	0
T2	296668	265110	0	0
T3	22818	22818	0	0
T5	91796	91796	0	0
T6	432	0	0	0
T7	44656	44656	0	0
T9	399133	397558	0	0
T10	567055	564306	0	0
T11	2640	0	0	0
T12	29543	29543	0	0
T13	0	17098	0	0
T14	0	6153	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140982772	752239	0	0
T2	296668	2236	0	0
T3	22818	0	0	0
T5	91796	0	0	0
T6	432	0	0	0
T7	44656	0	0	0
T9	399133	2093	0	0
T10	567055	2714	0	0
T11	2640	0	0	0
T12	29543	0	0	0
T13	17326	0	0	0
T16	0	11415	0	0
T25	0	6770	0	0
T27	0	283	0	0
T28	0	1028	0	0
T33	0	257	0	0
T41	0	1991	0	0
T47	0	3518	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140982772	752239	0	0
T2	296668	2236	0	0
T3	22818	0	0	0
T5	91796	0	0	0
T6	432	0	0	0
T7	44656	0	0	0
T9	399133	2093	0	0
T10	567055	2714	0	0
T11	2640	0	0	0
T12	29543	0	0	0
T13	17326	0	0	0
T16	0	11415	0	0
T25	0	6770	0	0
T27	0	283	0	0
T28	0	1028	0	0
T33	0	257	0	0
T41	0	1991	0	0
T47	0	3518	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140982772	113500253	0	0
T1	22080	22080	0	0
T2	296668	265110	0	0
T3	22818	22818	0	0
T5	91796	91796	0	0
T6	432	0	0	0
T7	44656	44656	0	0
T9	399133	397558	0	0
T10	567055	564306	0	0
T11	2640	0	0	0
T12	29543	29543	0	0
T13	0	17098	0	0
T14	0	6153	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140982772	113500253	0	0
T1	22080	22080	0	0
T2	296668	265110	0	0
T3	22818	22818	0	0
T5	91796	91796	0	0
T6	432	0	0	0
T7	44656	44656	0	0
T9	399133	397558	0	0
T10	567055	564306	0	0
T11	2640	0	0	0
T12	29543	29543	0	0
T13	0	17098	0	0
T14	0	6153	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140982772	752239	0	0
T2	296668	2236	0	0
T3	22818	0	0	0
T5	91796	0	0	0
T6	432	0	0	0
T7	44656	0	0	0
T9	399133	2093	0	0
T10	567055	2714	0	0
T11	2640	0	0	0
T12	29543	0	0	0
T13	17326	0	0	0
T16	0	11415	0	0
T25	0	6770	0	0
T27	0	283	0	0
T28	0	1028	0	0
T33	0	257	0	0
T41	0	1991	0	0
T47	0	3518	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140982772	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140982772	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140982772	752239	0	0
T2	296668	2236	0	0
T3	22818	0	0	0
T5	91796	0	0	0
T6	432	0	0	0
T7	44656	0	0	0
T9	399133	2093	0	0
T10	567055	2714	0	0
T11	2640	0	0	0
T12	29543	0	0	0
T13	17326	0	0	0
T16	0	11415	0	0
T25	0	6770	0	0
T27	0	283	0	0
T28	0	1028	0	0
T33	0	257	0	0
T41	0	1991	0	0
T47	0	3518	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140982772	752239	0	0
T2	296668	2236	0	0
T3	22818	0	0	0
T5	91796	0	0	0
T6	432	0	0	0
T7	44656	0	0	0
T9	399133	2093	0	0
T10	567055	2714	0	0
T11	2640	0	0	0
T12	29543	0	0	0
T13	17326	0	0	0
T16	0	11415	0	0
T25	0	6770	0	0
T27	0	283	0	0
T28	0	1028	0	0
T33	0	257	0	0
T41	0	1991	0	0
T47	0	3518	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140982772	752239	0	0
T2	296668	2236	0	0
T3	22818	0	0	0
T5	91796	0	0	0
T6	432	0	0	0
T7	44656	0	0	0
T9	399133	2093	0	0
T10	567055	2714	0	0
T11	2640	0	0	0
T12	29543	0	0	0
T13	17326	0	0	0
T16	0	11415	0	0
T25	0	6770	0	0
T27	0	283	0	0
T28	0	1028	0	0
T33	0	257	0	0
T41	0	1991	0	0
T47	0	3518	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	140982772	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140982772	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140982772	113500253	0	0
T1	22080	22080	0	0
T2	296668	265110	0	0
T3	22818	22818	0	0
T5	91796	91796	0	0
T6	432	0	0	0
T7	44656	44656	0	0
T9	399133	397558	0	0
T10	567055	564306	0	0
T11	2640	0	0	0
T12	29543	29543	0	0
T13	0	17098	0	0
T14	0	6153	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140982772	752239	0	0
T2	296668	2236	0	0
T3	22818	0	0	0
T5	91796	0	0	0
T6	432	0	0	0
T7	44656	0	0	0
T9	399133	2093	0	0
T10	567055	2714	0	0
T11	2640	0	0	0
T12	29543	0	0	0
T13	17326	0	0	0
T16	0	11415	0	0
T25	0	6770	0	0
T27	0	283	0	0
T28	0	1028	0	0
T33	0	257	0	0
T41	0	1991	0	0
T47	0	3518	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T6,T9
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414560164	414473306	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	414560164	2204481	0	0
GntImpliesValid_A	414560164	2204481	0	0
GrantKnown_A	414560164	414473306	0	0
IdxKnown_A	414560164	414473306	0	0
IndexIsCorrect_A	414560164	2204481	0	0
LockArbDecision_A	414560164	0	0	0
NoReadyValidNoGrant_A	414560164	0	0	0
ReadyAndValidImplyGrant_A	414560164	2204481	0	0
ReqAndReadyImplyGrant_A	414560164	2204481	0	0
ReqImpliesValid_A	414560164	2204481	0	0
ReqStaysHighUntilGranted0_M	414560164	0	0	0
RoundRobin_A	414560164	6	0	956
ValidKnown_A	414560164	414473306	0	0
gen_data_port_assertion.DataFlow_A	414560164	2204481	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414560164	414473306	0	0
T1	76906	76814	0	0
T2	120478	120472	0	0
T3	15104	15042	0	0
T4	1403	1343	0	0
T5	186784	186706	0	0
T6	4743	4677	0	0
T7	270958	270875	0	0
T8	3439	3367	0	0
T9	175321	175248	0	0
T10	287841	287836	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414560164	2204481	0	0
T1	76906	832	0	0
T2	120478	5825	0	0
T3	15104	832	0	0
T4	1403	0	0	0
T5	186784	832	0	0
T6	4743	6	0	0
T7	270958	832	0	0
T8	3439	832	0	0
T9	175321	5123	0	0
T10	287841	5256	0	0
T11	0	67	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414560164	2204481	0	0
T1	76906	832	0	0
T2	120478	5825	0	0
T3	15104	832	0	0
T4	1403	0	0	0
T5	186784	832	0	0
T6	4743	6	0	0
T7	270958	832	0	0
T8	3439	832	0	0
T9	175321	5123	0	0
T10	287841	5256	0	0
T11	0	67	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414560164	414473306	0	0
T1	76906	76814	0	0
T2	120478	120472	0	0
T3	15104	15042	0	0
T4	1403	1343	0	0
T5	186784	186706	0	0
T6	4743	4677	0	0
T7	270958	270875	0	0
T8	3439	3367	0	0
T9	175321	175248	0	0
T10	287841	287836	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414560164	414473306	0	0
T1	76906	76814	0	0
T2	120478	120472	0	0
T3	15104	15042	0	0
T4	1403	1343	0	0
T5	186784	186706	0	0
T6	4743	4677	0	0
T7	270958	270875	0	0
T8	3439	3367	0	0
T9	175321	175248	0	0
T10	287841	287836	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414560164	2204481	0	0
T1	76906	832	0	0
T2	120478	5825	0	0
T3	15104	832	0	0
T4	1403	0	0	0
T5	186784	832	0	0
T6	4743	6	0	0
T7	270958	832	0	0
T8	3439	832	0	0
T9	175321	5123	0	0
T10	287841	5256	0	0
T11	0	67	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414560164	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414560164	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414560164	2204481	0	0
T1	76906	832	0	0
T2	120478	5825	0	0
T3	15104	832	0	0
T4	1403	0	0	0
T5	186784	832	0	0
T6	4743	6	0	0
T7	270958	832	0	0
T8	3439	832	0	0
T9	175321	5123	0	0
T10	287841	5256	0	0
T11	0	67	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414560164	2204481	0	0
T1	76906	832	0	0
T2	120478	5825	0	0
T3	15104	832	0	0
T4	1403	0	0	0
T5	186784	832	0	0
T6	4743	6	0	0
T7	270958	832	0	0
T8	3439	832	0	0
T9	175321	5123	0	0
T10	287841	5256	0	0
T11	0	67	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414560164	2204481	0	0
T1	76906	832	0	0
T2	120478	5825	0	0
T3	15104	832	0	0
T4	1403	0	0	0
T5	186784	832	0	0
T6	4743	6	0	0
T7	270958	832	0	0
T8	3439	832	0	0
T9	175321	5123	0	0
T10	287841	5256	0	0
T11	0	67	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414560164	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414560164	6	0	956
T48	188249	2	0	1
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	4054	0	0	1
T54	59466	0	0	1
T55	314323	0	0	1
T56	128234	0	0	1
T57	63113	0	0	1
T58	1368	0	0	1
T59	260257	0	0	1
T60	13104	0	0	1
T61	97850	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414560164	414473306	0	0
T1	76906	76814	0	0
T2	120478	120472	0	0
T3	15104	15042	0	0
T4	1403	1343	0	0
T5	186784	186706	0	0
T6	4743	4677	0	0
T7	270958	270875	0	0
T8	3439	3367	0	0
T9	175321	175248	0	0
T10	287841	287836	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414560164	2204481	0	0
T1	76906	832	0	0
T2	120478	5825	0	0
T3	15104	832	0	0
T4	1403	0	0	0
T5	186784	832	0	0
T6	4743	6	0	0
T7	270958	832	0	0
T8	3439	832	0	0
T9	175321	5123	0	0
T10	287841	5256	0	0
T11	0	67	0	0