Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3420301	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4203229

1

T1

2892

T2

9440

T3

888

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4201091	1			T1	4075		T2	2995		T3	30
values[0x0]	1709836	1			T1	450		T2	3897		T3	426
values[0x1]	1712603	1			T1	429		T2	4032		T3	453

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2440965	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5182565

1

T1

3329

T2

9740

T3

893

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29067	1			T1	20		T2	50		T4	1
valid_sources[0x01]	27033	1			T1	13		T2	47		T4	1
valid_sources[0x02]	29364	1			T1	23		T2	46		T4	2
valid_sources[0x03]	30491	1			T1	22		T2	38		T4	3
valid_sources[0x04]	31837	1			T1	21		T2	45		T4	2
valid_sources[0x05]	30688	1			T1	19		T2	37		T3	1
valid_sources[0x06]	26164	1			T1	20		T2	51		T4	1
valid_sources[0x07]	26763	1			T1	11		T2	36		T4	1
valid_sources[0x08]	26742	1			T1	22		T2	38		T5	64
valid_sources[0x09]	26727	1			T1	21		T2	44		T4	2
valid_sources[0x0a]	27561	1			T1	25		T2	49		T4	1
valid_sources[0x0b]	28457	1			T1	23		T2	51		T3	1
valid_sources[0x0c]	29365	1			T1	20		T2	49		T5	77
valid_sources[0x0d]	32604	1			T1	18		T2	31		T4	1
valid_sources[0x0e]	28636	1			T1	13		T2	29		T4	3
valid_sources[0x0f]	29577	1			T1	20		T2	38		T4	1
valid_sources[0x10]	30355	1			T1	17		T2	43		T3	1
valid_sources[0x11]	30287	1			T1	15		T2	46		T4	1
valid_sources[0x12]	29560	1			T1	13		T2	33		T4	1
valid_sources[0x13]	27657	1			T1	21		T2	33		T5	104
valid_sources[0x14]	31235	1			T1	19		T2	38		T4	2
valid_sources[0x15]	26422	1			T1	30		T2	51		T4	2
valid_sources[0x16]	36399	1			T1	28		T2	49		T3	1
valid_sources[0x17]	29238	1			T1	25		T2	41		T4	2
valid_sources[0x18]	30909	1			T1	31		T2	34		T3	1
valid_sources[0x19]	29712	1			T1	17		T2	53		T5	85
valid_sources[0x1a]	30040	1			T1	18		T2	27		T4	3
valid_sources[0x1b]	29127	1			T1	23		T2	62		T4	4
valid_sources[0x1c]	27448	1			T1	22		T2	39		T4	2
valid_sources[0x1d]	31639	1			T1	17		T2	35		T4	3
valid_sources[0x1e]	27141	1			T1	25		T2	47		T4	1
valid_sources[0x1f]	30499	1			T1	19		T2	51		T4	3
valid_sources[0x20]	27441	1			T1	16		T2	43		T4	1
valid_sources[0x21]	26017	1			T1	30		T2	53		T3	1
valid_sources[0x22]	29570	1			T1	15		T2	48		T5	86
valid_sources[0x23]	42539	1			T1	16		T2	39		T4	1
valid_sources[0x24]	29030	1			T1	30		T2	35		T4	1
valid_sources[0x25]	28151	1			T1	13		T2	38		T4	2
valid_sources[0x26]	29709	1			T1	23		T2	33		T4	2
valid_sources[0x27]	28326	1			T1	25		T2	60		T4	3
valid_sources[0x28]	29078	1			T1	24		T2	38		T4	1
valid_sources[0x29]	27371	1			T1	27		T2	28		T4	1
valid_sources[0x2a]	29899	1			T1	14		T2	36		T4	2
valid_sources[0x2b]	28856	1			T1	23		T2	45		T5	87
valid_sources[0x2c]	29829	1			T1	28		T2	38		T4	1
valid_sources[0x2d]	27779	1			T1	21		T2	48		T4	1
valid_sources[0x2e]	29467	1			T1	16		T2	43		T5	97
valid_sources[0x2f]	28712	1			T1	13		T2	66		T4	3
valid_sources[0x30]	30892	1			T1	26		T2	43		T4	4
valid_sources[0x31]	27745	1			T1	26		T2	46		T4	1
valid_sources[0x32]	26578	1			T1	14		T2	43		T4	1
valid_sources[0x33]	35576	1			T1	23		T2	39		T4	2
valid_sources[0x34]	28481	1			T1	18		T2	26		T4	4
valid_sources[0x35]	27649	1			T1	24		T2	36		T3	1
valid_sources[0x36]	33346	1			T1	19		T2	36		T4	1
valid_sources[0x37]	27674	1			T1	17		T2	28		T4	4
valid_sources[0x38]	26397	1			T1	25		T2	49		T4	3
valid_sources[0x39]	28754	1			T1	15		T2	39		T4	1
valid_sources[0x3a]	30948	1			T1	12		T2	28		T4	1
valid_sources[0x3b]	26342	1			T1	19		T2	57		T4	1
valid_sources[0x3c]	29281	1			T1	15		T2	43		T4	2
valid_sources[0x3d]	27743	1			T1	29		T2	48		T4	6
valid_sources[0x3e]	31046	1			T1	21		T2	54		T5	91
valid_sources[0x3f]	30762	1			T1	16		T2	36		T4	1
valid_sources[0x40]	28505	1			T1	23		T2	34		T3	335
valid_sources[0x41]	36194	1			T1	16		T2	21		T4	2
valid_sources[0x42]	29967	1			T1	18		T2	38		T4	1
valid_sources[0x43]	30722	1			T1	14		T2	25		T4	2
valid_sources[0x44]	26183	1			T1	22		T2	37		T4	1
valid_sources[0x45]	27902	1			T1	16		T2	35		T4	1
valid_sources[0x46]	29019	1			T1	15		T2	51		T4	3
valid_sources[0x47]	27896	1			T1	17		T2	39		T5	55
valid_sources[0x48]	28468	1			T1	18		T2	38		T3	3
valid_sources[0x49]	28899	1			T1	17		T2	30		T4	1
valid_sources[0x4a]	29876	1			T1	18		T2	37		T4	1
valid_sources[0x4b]	28778	1			T1	14		T2	52		T4	1
valid_sources[0x4c]	36715	1			T1	19		T2	36		T3	19
valid_sources[0x4d]	26256	1			T1	16		T2	45		T5	90
valid_sources[0x4e]	30777	1			T1	12		T2	42		T4	1
valid_sources[0x4f]	28524	1			T1	19		T2	38		T4	2
valid_sources[0x50]	28292	1			T1	17		T2	38		T4	2
valid_sources[0x51]	28592	1			T1	26		T2	29		T5	77
valid_sources[0x52]	26289	1			T1	24		T2	44		T4	1
valid_sources[0x53]	26987	1			T1	26		T2	43		T4	1
valid_sources[0x54]	30740	1			T1	15		T2	57		T4	1
valid_sources[0x55]	32291	1			T1	29		T2	33		T5	80
valid_sources[0x56]	31235	1			T1	20		T2	47		T3	15
valid_sources[0x57]	29528	1			T1	19		T2	37		T4	7
valid_sources[0x58]	29541	1			T1	16		T2	43		T4	3
valid_sources[0x59]	32061	1			T1	27		T2	49		T4	2
valid_sources[0x5a]	33265	1			T1	18		T2	35		T5	56
valid_sources[0x5b]	25853	1			T1	24		T2	56		T4	2
valid_sources[0x5c]	27287	1			T1	18		T2	38		T4	2
valid_sources[0x5d]	27269	1			T1	21		T2	42		T3	1
valid_sources[0x5e]	27643	1			T1	14		T2	36		T4	3
valid_sources[0x5f]	33507	1			T1	28		T2	57		T3	1
valid_sources[0x60]	33121	1			T1	20		T2	52		T4	1
valid_sources[0x61]	28506	1			T1	19		T2	45		T4	1
valid_sources[0x62]	29451	1			T1	26		T2	65		T5	60
valid_sources[0x63]	31955	1			T1	15		T2	38		T4	1
valid_sources[0x64]	26508	1			T1	21		T2	32		T4	3
valid_sources[0x65]	28651	1			T1	15		T2	42		T3	1
valid_sources[0x66]	33433	1			T1	24		T2	44		T4	2
valid_sources[0x67]	30320	1			T1	27		T2	37		T4	2
valid_sources[0x68]	31100	1			T1	21		T2	41		T4	2
valid_sources[0x69]	26759	1			T1	13		T2	44		T4	1
valid_sources[0x6a]	32287	1			T1	21		T2	38		T5	82
valid_sources[0x6b]	28415	1			T1	22		T2	51		T4	1
valid_sources[0x6c]	27382	1			T1	20		T2	52		T4	1
valid_sources[0x6d]	27704	1			T1	15		T2	38		T4	1
valid_sources[0x6e]	27304	1			T1	21		T2	50		T4	3
valid_sources[0x6f]	28707	1			T1	11		T2	52		T4	3
valid_sources[0x70]	30358	1			T1	19		T2	49		T4	1
valid_sources[0x71]	26643	1			T1	17		T2	49		T4	2
valid_sources[0x72]	29135	1			T1	21		T2	47		T5	101
valid_sources[0x73]	30379	1			T1	17		T2	40		T4	1
valid_sources[0x74]	28532	1			T1	20		T2	46		T5	98
valid_sources[0x75]	36190	1			T1	17		T2	33		T4	1
valid_sources[0x76]	29495	1			T1	15		T2	49		T4	2
valid_sources[0x77]	40472	1			T1	13		T2	27		T4	3
valid_sources[0x78]	29491	1			T1	15		T2	38		T4	1
valid_sources[0x79]	27394	1			T1	19		T2	33		T4	1
valid_sources[0x7a]	27905	1			T1	18		T2	64		T5	74
valid_sources[0x7b]	29786	1			T1	14		T2	36		T5	101
valid_sources[0x7c]	27369	1			T1	33		T2	34		T4	1
valid_sources[0x7d]	33754	1			T1	16		T2	32		T4	2
valid_sources[0x7e]	27986	1			T1	28		T2	28		T4	2
valid_sources[0x7f]	28749	1			T1	23		T2	40		T4	1
valid_sources[0x80]	33500	1			T1	15		T2	31		T5	92

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1099023

1

T1

2018

T2

1556

T3

12

values[0x0]

all_enables

biggest_size

1563104

1

T1

448

T2

3882

T3

424

values[0x1]

all_enables

biggest_size

1541102

1

T1

426

T2

4002

T3

452