Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3439880

1

T1

2062

T2

1484

T3

21

full_word

4204339

1

T1

2892

T2

9440

T3

888

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7643849	1			T1	4954		T2	10924		T3	909
auto[TlIntgErrCmd]	130	1			T73	4		T106	5		T107	7
auto[TlIntgErrData]	116	1			T73	8		T106	12		T107	6
auto[TlIntgErrBoth]	124	1			T73	8		T106	13		T107	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4204094

1

T1

4075

T2

2995

T3

30

auto[1]

3440125

1

T1

879

T2

7929

T3

879

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3104638	1			T1	2057		T2	1439		T3	18
auto[TlIntgErrNone]	partial	auto[1]	334897	1			T1	5		T2	45		T3	3
auto[TlIntgErrNone]	full_word	auto[0]	1099283	1			T1	2018		T2	1556		T3	12
auto[TlIntgErrNone]	full_word	auto[1]	3105031	1			T1	874		T2	7884		T3	876
auto[TlIntgErrCmd]	partial	auto[0]	58	1			T73	3		T106	1		T107	3
auto[TlIntgErrCmd]	partial	auto[1]	62	1			T73	1		T106	3		T107	3
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T124	1		T180	1		T181	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T106	1		T107	1		T180	1
auto[TlIntgErrData]	partial	auto[0]	55	1			T73	6		T106	2		T107	3
auto[TlIntgErrData]	partial	auto[1]	53	1			T73	2		T106	8		T107	2
auto[TlIntgErrData]	full_word	auto[0]	2	1			T182	1		T183	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	6	1			T106	2		T107	1		T181	1
auto[TlIntgErrBoth]	partial	auto[0]	53	1			T73	4		T106	5		T124	1
auto[TlIntgErrBoth]	partial	auto[1]	64	1			T73	4		T106	6		T107	6
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T106	2		T107	1		T125	1