Unified Coverage Report :: Module :: prim_pulse_sync

Module : prim_pulse_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_readbuf_watermark_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_flash_readbuf_flip_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_upload.u_payloadptr_clr_psync	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_upload.u_payloadptr_clr_psync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.37	100.00	86.11		100.00	95.74	100.00	u_upload

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T6,T7
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T6,T7

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T6,T7
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T6,T7

---

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1325609433	2740	0	0
SrcPulseCheck_M	459047547	2740	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1325609433	2740	0	0
T2	184693	9	0	0
T3	15354	0	0	0
T4	346651	0	0	0
T5	607261	0	0	0
T6	221020	21	0	0
T7	357917	9	0	0
T8	270827	0	0	0
T9	86452	0	0	0
T10	44834	4	0	0
T11	55216	0	0	0
T12	1640370	16	0	0
T13	0	13	0	0
T14	0	4	0	0
T22	200260	5	0	0
T23	396296	0	0	0
T24	23680	0	0	0
T25	1258568	0	0	0
T26	3558	0	0	0
T27	3062	0	0	0
T28	14704	7	0	0
T29	1926	0	0	0
T40	0	4	0	0
T44	73974	4	0	0
T45	0	11	0	0
T69	0	2	0	0
T162	0	7	0	0
T163	0	7	0	0
T164	0	1	0	0
T165	0	3	0	0
T166	0	9	0	0
T167	0	7	0	0
T168	0	7	0	0
T169	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	459047547	2740	0	0
T2	298811	9	0	0
T3	4160	0	0	0
T4	42600	0	0	0
T5	86433	0	0	0
T6	104899	21	0	0
T7	442358	9	0	0
T8	38103	0	0	0
T9	160016	0	0	0
T10	37808	4	0	0
T11	6368	0	0	0
T12	274604	16	0	0
T13	0	13	0	0
T14	0	4	0	0
T22	671922	5	0	0
T23	63614	0	0	0
T24	12480	0	0	0
T25	178848	0	0	0
T27	288	0	0	0
T28	32678	7	0	0
T40	252242	4	0	0
T44	117588	4	0	0
T45	0	11	0	0
T69	0	2	0	0
T162	0	7	0	0
T163	0	7	0	0
T164	0	1	0	0
T165	0	3	0	0
T166	0	9	0	0
T167	0	7	0	0
T168	0	7	0	0
T169	0	5	0	0
T170	26022	0	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T44,T28,T45
1	0	Covered	T44,T28,T45
1	1	Covered	T44,T28,T45

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T44,T28,T45
1	0	Covered	T44,T28,T45
1	1	Covered	T44,T28,T45

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	441869811	197	0	0
SrcPulseCheck_M	153015849	197	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441869811	197	0	0
T12	820185	0	0	0
T22	100130	0	0	0
T23	198148	0	0	0
T24	11840	0	0	0
T25	629284	0	0	0
T26	1779	0	0	0
T27	1531	0	0	0
T28	7352	2	0	0
T29	963	0	0	0
T44	36987	2	0	0
T45	0	6	0	0
T162	0	2	0	0
T163	0	2	0	0
T164	0	1	0	0
T165	0	2	0	0
T166	0	5	0	0
T167	0	2	0	0
T168	0	4	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	153015849	197	0	0
T12	137302	0	0	0
T22	335961	0	0	0
T23	31807	0	0	0
T24	6240	0	0	0
T25	89424	0	0	0
T27	144	0	0	0
T28	16339	2	0	0
T40	126121	0	0	0
T44	58794	2	0	0
T45	0	6	0	0
T162	0	2	0	0
T163	0	2	0	0
T164	0	1	0	0
T165	0	2	0	0
T166	0	5	0	0
T167	0	2	0	0
T168	0	4	0	0
T170	13011	0	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T44,T28,T45
1	0	Covered	T44,T28,T45
1	1	Covered	T44,T28,T45

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T44,T28,T45
1	0	Covered	T44,T28,T45
1	1	Covered	T44,T28,T45

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	441869811	331	0	0
SrcPulseCheck_M	153015849	331	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441869811	331	0	0
T12	820185	0	0	0
T22	100130	0	0	0
T23	198148	0	0	0
T24	11840	0	0	0
T25	629284	0	0	0
T26	1779	0	0	0
T27	1531	0	0	0
T28	7352	5	0	0
T29	963	0	0	0
T44	36987	2	0	0
T45	0	5	0	0
T162	0	5	0	0
T163	0	5	0	0
T165	0	1	0	0
T166	0	4	0	0
T167	0	5	0	0
T168	0	3	0	0
T169	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	153015849	331	0	0
T12	137302	0	0	0
T22	335961	0	0	0
T23	31807	0	0	0
T24	6240	0	0	0
T25	89424	0	0	0
T27	144	0	0	0
T28	16339	5	0	0
T40	126121	0	0	0
T44	58794	2	0	0
T45	0	5	0	0
T162	0	5	0	0
T163	0	5	0	0
T165	0	1	0	0
T166	0	4	0	0
T167	0	5	0	0
T168	0	3	0	0
T169	0	5	0	0
T170	13011	0	0	0

Line Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T6,T7
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T6,T7

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T6,T7
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T6,T7

---

Branch Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	441869811	2212	0	0
SrcPulseCheck_M	153015849	2212	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441869811	2212	0	0
T2	184693	9	0	0
T3	15354	0	0	0
T4	346651	0	0	0
T5	607261	0	0	0
T6	221020	21	0	0
T7	357917	9	0	0
T8	270827	0	0	0
T9	86452	0	0	0
T10	44834	4	0	0
T11	55216	0	0	0
T12	0	16	0	0
T13	0	13	0	0
T14	0	4	0	0
T22	0	5	0	0
T40	0	4	0	0
T69	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	153015849	2212	0	0
T2	298811	9	0	0
T3	4160	0	0	0
T4	42600	0	0	0
T5	86433	0	0	0
T6	104899	21	0	0
T7	442358	9	0	0
T8	38103	0	0	0
T9	160016	0	0	0
T10	37808	4	0	0
T11	6368	0	0	0
T12	0	16	0	0
T13	0	13	0	0
T14	0	4	0	0
T22	0	5	0	0
T40	0	4	0	0
T69	0	2	0	0