Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T31,T12,T22
1	0	Covered	T31,T12,T22

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T31,T32
1	0	Unreachable
1	1	Covered	T31,T12,T22

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T6,T7
1	0	Covered	T2,T6,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T6,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T6,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	747901509	593468424	0	0
CheckNGreaterZero_A	2862	2862	0	0
GntImpliesReady_A	747901509	3677872	0	0
GntImpliesValid_A	747901509	3677872	0	0
GrantKnown_A	747901509	593468424	0	0
IdxKnown_A	747901509	593468424	0	0
IndexIsCorrect_A	747901509	3677872	0	0
LockArbDecision_A	747901509	0	0	0
NoReadyValidNoGrant_A	747901509	0	0	0
ReadyAndValidImplyGrant_A	747901509	3677872	0	0
ReqAndReadyImplyGrant_A	747901509	3677872	0	0
ReqImpliesValid_A	747901509	3677872	0	0
ReqStaysHighUntilGranted0_M	747901509	0	0	0
RoundRobin_A	747901509	4	0	954
ValidKnown_A	747901509	593468424	0	0
gen_data_port_assertion.DataFlow_A	747901509	3677872	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	747901509	593468424	0	0
T1	79685	79585	0	0
T2	483504	480519	0	0
T3	19514	19431	0	0
T4	431851	388698	0	0
T5	780127	693154	0	0
T6	430818	325548	0	0
T7	1242633	798143	0	0
T8	347033	308751	0	0
T9	406484	246414	0	0
T10	120450	82571	0	0
T11	6368	6368	0	0
T12	0	387160	0	0
T22	0	88152	0	0
T27	0	144	0	0
T31	592	592	0	0
T32	0	288	0	0
T33	0	1720	0	0
T34	0	792	0	0
T35	0	52552	0	0
T36	0	63240	0	0
T47	129646	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2862	2862	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	747901509	3677872	0	0
T1	60528	832	0	0
T2	483504	10560	0	0
T3	19514	832	0	0
T4	389251	0	0	0
T5	693694	832	0	0
T6	325919	23110	0	0
T7	800275	10761	0	0
T8	308930	832	0	0
T9	246468	832	0	0
T10	82642	4548	0	0
T11	6368	832	0	0
T12	137302	16383	0	0
T13	0	11414	0	0
T14	0	3120	0	0
T22	0	4520	0	0
T31	592	26	0	0
T32	288	0	0	0
T33	0	135	0	0
T36	0	2622	0	0
T40	0	6408	0	0
T43	35321	0	0	0
T44	58794	0	0	0
T46	0	3801	0	0
T47	129646	0	0	0
T48	9744	0	0	0
T51	2912	0	0	0
T52	2436	0	0	0
T53	0	43	0	0
T54	24672	0	0	0
T55	0	18	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	747901509	3677872	0	0
T1	60528	832	0	0
T2	483504	10560	0	0
T3	19514	832	0	0
T4	389251	0	0	0
T5	693694	832	0	0
T6	325919	23110	0	0
T7	800275	10761	0	0
T8	308930	832	0	0
T9	246468	832	0	0
T10	82642	4548	0	0
T11	6368	832	0	0
T12	137302	16383	0	0
T13	0	11414	0	0
T14	0	3120	0	0
T22	0	4520	0	0
T31	592	26	0	0
T32	288	0	0	0
T33	0	135	0	0
T36	0	2622	0	0
T40	0	6408	0	0
T43	35321	0	0	0
T44	58794	0	0	0
T46	0	3801	0	0
T47	129646	0	0	0
T48	9744	0	0	0
T51	2912	0	0	0
T52	2436	0	0	0
T53	0	43	0	0
T54	24672	0	0	0
T55	0	18	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	747901509	593468424	0	0
T1	79685	79585	0	0
T2	483504	480519	0	0
T3	19514	19431	0	0
T4	431851	388698	0	0
T5	780127	693154	0	0
T6	430818	325548	0	0
T7	1242633	798143	0	0
T8	347033	308751	0	0
T9	406484	246414	0	0
T10	120450	82571	0	0
T11	6368	6368	0	0
T12	0	387160	0	0
T22	0	88152	0	0
T27	0	144	0	0
T31	592	592	0	0
T32	0	288	0	0
T33	0	1720	0	0
T34	0	792	0	0
T35	0	52552	0	0
T36	0	63240	0	0
T47	129646	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	747901509	593468424	0	0
T1	79685	79585	0	0
T2	483504	480519	0	0
T3	19514	19431	0	0
T4	431851	388698	0	0
T5	780127	693154	0	0
T6	430818	325548	0	0
T7	1242633	798143	0	0
T8	347033	308751	0	0
T9	406484	246414	0	0
T10	120450	82571	0	0
T11	6368	6368	0	0
T12	0	387160	0	0
T22	0	88152	0	0
T27	0	144	0	0
T31	592	592	0	0
T32	0	288	0	0
T33	0	1720	0	0
T34	0	792	0	0
T35	0	52552	0	0
T36	0	63240	0	0
T47	129646	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	747901509	3677872	0	0
T1	60528	832	0	0
T2	483504	10560	0	0
T3	19514	832	0	0
T4	389251	0	0	0
T5	693694	832	0	0
T6	325919	23110	0	0
T7	800275	10761	0	0
T8	308930	832	0	0
T9	246468	832	0	0
T10	82642	4548	0	0
T11	6368	832	0	0
T12	137302	16383	0	0
T13	0	11414	0	0
T14	0	3120	0	0
T22	0	4520	0	0
T31	592	26	0	0
T32	288	0	0	0
T33	0	135	0	0
T36	0	2622	0	0
T40	0	6408	0	0
T43	35321	0	0	0
T44	58794	0	0	0
T46	0	3801	0	0
T47	129646	0	0	0
T48	9744	0	0	0
T51	2912	0	0	0
T52	2436	0	0	0
T53	0	43	0	0
T54	24672	0	0	0
T55	0	18	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	747901509	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	747901509	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	747901509	3677872	0	0
T1	60528	832	0	0
T2	483504	10560	0	0
T3	19514	832	0	0
T4	389251	0	0	0
T5	693694	832	0	0
T6	325919	23110	0	0
T7	800275	10761	0	0
T8	308930	832	0	0
T9	246468	832	0	0
T10	82642	4548	0	0
T11	6368	832	0	0
T12	137302	16383	0	0
T13	0	11414	0	0
T14	0	3120	0	0
T22	0	4520	0	0
T31	592	26	0	0
T32	288	0	0	0
T33	0	135	0	0
T36	0	2622	0	0
T40	0	6408	0	0
T43	35321	0	0	0
T44	58794	0	0	0
T46	0	3801	0	0
T47	129646	0	0	0
T48	9744	0	0	0
T51	2912	0	0	0
T52	2436	0	0	0
T53	0	43	0	0
T54	24672	0	0	0
T55	0	18	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	747901509	3677872	0	0
T1	60528	832	0	0
T2	483504	10560	0	0
T3	19514	832	0	0
T4	389251	0	0	0
T5	693694	832	0	0
T6	325919	23110	0	0
T7	800275	10761	0	0
T8	308930	832	0	0
T9	246468	832	0	0
T10	82642	4548	0	0
T11	6368	832	0	0
T12	137302	16383	0	0
T13	0	11414	0	0
T14	0	3120	0	0
T22	0	4520	0	0
T31	592	26	0	0
T32	288	0	0	0
T33	0	135	0	0
T36	0	2622	0	0
T40	0	6408	0	0
T43	35321	0	0	0
T44	58794	0	0	0
T46	0	3801	0	0
T47	129646	0	0	0
T48	9744	0	0	0
T51	2912	0	0	0
T52	2436	0	0	0
T53	0	43	0	0
T54	24672	0	0	0
T55	0	18	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	747901509	3677872	0	0
T1	60528	832	0	0
T2	483504	10560	0	0
T3	19514	832	0	0
T4	389251	0	0	0
T5	693694	832	0	0
T6	325919	23110	0	0
T7	800275	10761	0	0
T8	308930	832	0	0
T9	246468	832	0	0
T10	82642	4548	0	0
T11	6368	832	0	0
T12	137302	16383	0	0
T13	0	11414	0	0
T14	0	3120	0	0
T22	0	4520	0	0
T31	592	26	0	0
T32	288	0	0	0
T33	0	135	0	0
T36	0	2622	0	0
T40	0	6408	0	0
T43	35321	0	0	0
T44	58794	0	0	0
T46	0	3801	0	0
T47	129646	0	0	0
T48	9744	0	0	0
T51	2912	0	0	0
T52	2436	0	0	0
T53	0	43	0	0
T54	24672	0	0	0
T55	0	18	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	747901509	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	747901509	4	0	954
T56	170956	1	0	1
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	172891	0	0	1
T61	541440	0	0	1
T62	123708	0	0	1
T63	465193	0	0	1
T64	227401	0	0	1
T65	234220	0	0	1
T66	1853	0	0	1
T67	6787	0	0	1
T68	954	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	747901509	593468424	0	0
T1	79685	79585	0	0
T2	483504	480519	0	0
T3	19514	19431	0	0
T4	431851	388698	0	0
T5	780127	693154	0	0
T6	430818	325548	0	0
T7	1242633	798143	0	0
T8	347033	308751	0	0
T9	406484	246414	0	0
T10	120450	82571	0	0
T11	6368	6368	0	0
T12	0	387160	0	0
T22	0	88152	0	0
T27	0	144	0	0
T31	592	592	0	0
T32	0	288	0	0
T33	0	1720	0	0
T34	0	792	0	0
T35	0	52552	0	0
T36	0	63240	0	0
T47	129646	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	747901509	3677872	0	0
T1	60528	832	0	0
T2	483504	10560	0	0
T3	19514	832	0	0
T4	389251	0	0	0
T5	693694	832	0	0
T6	325919	23110	0	0
T7	800275	10761	0	0
T8	308930	832	0	0
T9	246468	832	0	0
T10	82642	4548	0	0
T11	6368	832	0	0
T12	137302	16383	0	0
T13	0	11414	0	0
T14	0	3120	0	0
T22	0	4520	0	0
T31	592	26	0	0
T32	288	0	0	0
T33	0	135	0	0
T36	0	2622	0	0
T40	0	6408	0	0
T43	35321	0	0	0
T44	58794	0	0	0
T46	0	3801	0	0
T47	129646	0	0	0
T48	9744	0	0	0
T51	2912	0	0	0
T52	2436	0	0	0
T53	0	43	0	0
T54	24672	0	0	0
T55	0	18	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T31,T12,T22
1	0	Covered	T31,T12,T22

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T31,T32
1	0	Unreachable
1	1	Covered	T31,T12,T22

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T31,T12,T22
0	0	1	Unreachable
0	0	0	Covered	T4,T31,T32

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T31,T12,T22
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T31,T12,T22
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	153015849	30810840	0	0
CheckNGreaterZero_A	954	954	0	0
GntImpliesReady_A	153015849	646067	0	0
GntImpliesValid_A	153015849	646067	0	0
GrantKnown_A	153015849	30810840	0	0
IdxKnown_A	153015849	30810840	0	0
IndexIsCorrect_A	153015849	646067	0	0
LockArbDecision_A	153015849	0	0	0
NoReadyValidNoGrant_A	153015849	0	0	0
ReadyAndValidImplyGrant_A	153015849	646067	0	0
ReqAndReadyImplyGrant_A	153015849	646067	0	0
ReqImpliesValid_A	153015849	646067	0	0
ReqStaysHighUntilGranted0_M	153015849	0	0	0
RoundRobin_A	153015849	0	0	0
ValidKnown_A	153015849	30810840	0	0
gen_data_port_assertion.DataFlow_A	153015849	646067	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153015849	30810840	0	0
T4	42600	42112	0	0
T5	86433	0	0	0
T6	104899	0	0	0
T7	442358	0	0	0
T8	38103	0	0	0
T9	160016	0	0	0
T10	37808	0	0	0
T11	6368	0	0	0
T12	0	387160	0	0
T22	0	88152	0	0
T27	0	144	0	0
T31	592	592	0	0
T32	0	288	0	0
T33	0	1720	0	0
T34	0	792	0	0
T35	0	52552	0	0
T36	0	63240	0	0
T47	129646	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153015849	646067	0	0
T12	137302	6764	0	0
T13	0	5209	0	0
T14	0	2345	0	0
T22	0	3483	0	0
T31	592	26	0	0
T32	288	0	0	0
T33	0	135	0	0
T36	0	2622	0	0
T43	35321	0	0	0
T44	58794	0	0	0
T46	0	3801	0	0
T47	129646	0	0	0
T48	9744	0	0	0
T51	2912	0	0	0
T52	2436	0	0	0
T53	0	43	0	0
T54	24672	0	0	0
T55	0	18	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153015849	646067	0	0
T12	137302	6764	0	0
T13	0	5209	0	0
T14	0	2345	0	0
T22	0	3483	0	0
T31	592	26	0	0
T32	288	0	0	0
T33	0	135	0	0
T36	0	2622	0	0
T43	35321	0	0	0
T44	58794	0	0	0
T46	0	3801	0	0
T47	129646	0	0	0
T48	9744	0	0	0
T51	2912	0	0	0
T52	2436	0	0	0
T53	0	43	0	0
T54	24672	0	0	0
T55	0	18	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153015849	30810840	0	0
T4	42600	42112	0	0
T5	86433	0	0	0
T6	104899	0	0	0
T7	442358	0	0	0
T8	38103	0	0	0
T9	160016	0	0	0
T10	37808	0	0	0
T11	6368	0	0	0
T12	0	387160	0	0
T22	0	88152	0	0
T27	0	144	0	0
T31	592	592	0	0
T32	0	288	0	0
T33	0	1720	0	0
T34	0	792	0	0
T35	0	52552	0	0
T36	0	63240	0	0
T47	129646	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153015849	30810840	0	0
T4	42600	42112	0	0
T5	86433	0	0	0
T6	104899	0	0	0
T7	442358	0	0	0
T8	38103	0	0	0
T9	160016	0	0	0
T10	37808	0	0	0
T11	6368	0	0	0
T12	0	387160	0	0
T22	0	88152	0	0
T27	0	144	0	0
T31	592	592	0	0
T32	0	288	0	0
T33	0	1720	0	0
T34	0	792	0	0
T35	0	52552	0	0
T36	0	63240	0	0
T47	129646	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153015849	646067	0	0
T12	137302	6764	0	0
T13	0	5209	0	0
T14	0	2345	0	0
T22	0	3483	0	0
T31	592	26	0	0
T32	288	0	0	0
T33	0	135	0	0
T36	0	2622	0	0
T43	35321	0	0	0
T44	58794	0	0	0
T46	0	3801	0	0
T47	129646	0	0	0
T48	9744	0	0	0
T51	2912	0	0	0
T52	2436	0	0	0
T53	0	43	0	0
T54	24672	0	0	0
T55	0	18	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153015849	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153015849	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153015849	646067	0	0
T12	137302	6764	0	0
T13	0	5209	0	0
T14	0	2345	0	0
T22	0	3483	0	0
T31	592	26	0	0
T32	288	0	0	0
T33	0	135	0	0
T36	0	2622	0	0
T43	35321	0	0	0
T44	58794	0	0	0
T46	0	3801	0	0
T47	129646	0	0	0
T48	9744	0	0	0
T51	2912	0	0	0
T52	2436	0	0	0
T53	0	43	0	0
T54	24672	0	0	0
T55	0	18	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153015849	646067	0	0
T12	137302	6764	0	0
T13	0	5209	0	0
T14	0	2345	0	0
T22	0	3483	0	0
T31	592	26	0	0
T32	288	0	0	0
T33	0	135	0	0
T36	0	2622	0	0
T43	35321	0	0	0
T44	58794	0	0	0
T46	0	3801	0	0
T47	129646	0	0	0
T48	9744	0	0	0
T51	2912	0	0	0
T52	2436	0	0	0
T53	0	43	0	0
T54	24672	0	0	0
T55	0	18	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153015849	646067	0	0
T12	137302	6764	0	0
T13	0	5209	0	0
T14	0	2345	0	0
T22	0	3483	0	0
T31	592	26	0	0
T32	288	0	0	0
T33	0	135	0	0
T36	0	2622	0	0
T43	35321	0	0	0
T44	58794	0	0	0
T46	0	3801	0	0
T47	129646	0	0	0
T48	9744	0	0	0
T51	2912	0	0	0
T52	2436	0	0	0
T53	0	43	0	0
T54	24672	0	0	0
T55	0	18	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	153015849	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153015849	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153015849	30810840	0	0
T4	42600	42112	0	0
T5	86433	0	0	0
T6	104899	0	0	0
T7	442358	0	0	0
T8	38103	0	0	0
T9	160016	0	0	0
T10	37808	0	0	0
T11	6368	0	0	0
T12	0	387160	0	0
T22	0	88152	0	0
T27	0	144	0	0
T31	592	592	0	0
T32	0	288	0	0
T33	0	1720	0	0
T34	0	792	0	0
T35	0	52552	0	0
T36	0	63240	0	0
T47	129646	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153015849	646067	0	0
T12	137302	6764	0	0
T13	0	5209	0	0
T14	0	2345	0	0
T22	0	3483	0	0
T31	592	26	0	0
T32	288	0	0	0
T33	0	135	0	0
T36	0	2622	0	0
T43	35321	0	0	0
T44	58794	0	0	0
T46	0	3801	0	0
T47	129646	0	0	0
T48	9744	0	0	0
T51	2912	0	0	0
T52	2436	0	0	0
T53	0	43	0	0
T54	24672	0	0	0
T55	0	18	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T6,T7
1	0	Covered	T2,T6,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T6,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T6,T7
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	153015849	120875202	0	0
CheckNGreaterZero_A	954	954	0	0
GntImpliesReady_A	153015849	791828	0	0
GntImpliesValid_A	153015849	791828	0	0
GrantKnown_A	153015849	120875202	0	0
IdxKnown_A	153015849	120875202	0	0
IndexIsCorrect_A	153015849	791828	0	0
LockArbDecision_A	153015849	0	0	0
NoReadyValidNoGrant_A	153015849	0	0	0
ReadyAndValidImplyGrant_A	153015849	791828	0	0
ReqAndReadyImplyGrant_A	153015849	791828	0	0
ReqImpliesValid_A	153015849	791828	0	0
ReqStaysHighUntilGranted0_M	153015849	0	0	0
RoundRobin_A	153015849	0	0	0
ValidKnown_A	153015849	120875202	0	0
gen_data_port_assertion.DataFlow_A	153015849	791828	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153015849	120875202	0	0
T1	19157	19157	0	0
T2	298811	295834	0	0
T3	4160	4160	0	0
T4	42600	0	0	0
T5	86433	85952	0	0
T6	104899	104536	0	0
T7	442358	440231	0	0
T8	38103	37976	0	0
T9	160016	160016	0	0
T10	37808	37808	0	0
T11	0	6368	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153015849	791828	0	0
T2	298811	2833	0	0
T3	4160	0	0	0
T4	42600	0	0	0
T5	86433	0	0	0
T6	104899	11713	0	0
T7	442358	1523	0	0
T8	38103	0	0	0
T9	160016	0	0	0
T10	37808	3584	0	0
T11	6368	0	0	0
T12	0	9619	0	0
T13	0	6205	0	0
T14	0	775	0	0
T22	0	1037	0	0
T40	0	6408	0	0
T69	0	4	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153015849	791828	0	0
T2	298811	2833	0	0
T3	4160	0	0	0
T4	42600	0	0	0
T5	86433	0	0	0
T6	104899	11713	0	0
T7	442358	1523	0	0
T8	38103	0	0	0
T9	160016	0	0	0
T10	37808	3584	0	0
T11	6368	0	0	0
T12	0	9619	0	0
T13	0	6205	0	0
T14	0	775	0	0
T22	0	1037	0	0
T40	0	6408	0	0
T69	0	4	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153015849	120875202	0	0
T1	19157	19157	0	0
T2	298811	295834	0	0
T3	4160	4160	0	0
T4	42600	0	0	0
T5	86433	85952	0	0
T6	104899	104536	0	0
T7	442358	440231	0	0
T8	38103	37976	0	0
T9	160016	160016	0	0
T10	37808	37808	0	0
T11	0	6368	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153015849	120875202	0	0
T1	19157	19157	0	0
T2	298811	295834	0	0
T3	4160	4160	0	0
T4	42600	0	0	0
T5	86433	85952	0	0
T6	104899	104536	0	0
T7	442358	440231	0	0
T8	38103	37976	0	0
T9	160016	160016	0	0
T10	37808	37808	0	0
T11	0	6368	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153015849	791828	0	0
T2	298811	2833	0	0
T3	4160	0	0	0
T4	42600	0	0	0
T5	86433	0	0	0
T6	104899	11713	0	0
T7	442358	1523	0	0
T8	38103	0	0	0
T9	160016	0	0	0
T10	37808	3584	0	0
T11	6368	0	0	0
T12	0	9619	0	0
T13	0	6205	0	0
T14	0	775	0	0
T22	0	1037	0	0
T40	0	6408	0	0
T69	0	4	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153015849	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153015849	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153015849	791828	0	0
T2	298811	2833	0	0
T3	4160	0	0	0
T4	42600	0	0	0
T5	86433	0	0	0
T6	104899	11713	0	0
T7	442358	1523	0	0
T8	38103	0	0	0
T9	160016	0	0	0
T10	37808	3584	0	0
T11	6368	0	0	0
T12	0	9619	0	0
T13	0	6205	0	0
T14	0	775	0	0
T22	0	1037	0	0
T40	0	6408	0	0
T69	0	4	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153015849	791828	0	0
T2	298811	2833	0	0
T3	4160	0	0	0
T4	42600	0	0	0
T5	86433	0	0	0
T6	104899	11713	0	0
T7	442358	1523	0	0
T8	38103	0	0	0
T9	160016	0	0	0
T10	37808	3584	0	0
T11	6368	0	0	0
T12	0	9619	0	0
T13	0	6205	0	0
T14	0	775	0	0
T22	0	1037	0	0
T40	0	6408	0	0
T69	0	4	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153015849	791828	0	0
T2	298811	2833	0	0
T3	4160	0	0	0
T4	42600	0	0	0
T5	86433	0	0	0
T6	104899	11713	0	0
T7	442358	1523	0	0
T8	38103	0	0	0
T9	160016	0	0	0
T10	37808	3584	0	0
T11	6368	0	0	0
T12	0	9619	0	0
T13	0	6205	0	0
T14	0	775	0	0
T22	0	1037	0	0
T40	0	6408	0	0
T69	0	4	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	153015849	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153015849	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153015849	120875202	0	0
T1	19157	19157	0	0
T2	298811	295834	0	0
T3	4160	4160	0	0
T4	42600	0	0	0
T5	86433	85952	0	0
T6	104899	104536	0	0
T7	442358	440231	0	0
T8	38103	37976	0	0
T9	160016	160016	0	0
T10	37808	37808	0	0
T11	0	6368	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153015849	791828	0	0
T2	298811	2833	0	0
T3	4160	0	0	0
T4	42600	0	0	0
T5	86433	0	0	0
T6	104899	11713	0	0
T7	442358	1523	0	0
T8	38103	0	0	0
T9	160016	0	0	0
T10	37808	3584	0	0
T11	6368	0	0	0
T12	0	9619	0	0
T13	0	6205	0	0
T14	0	775	0	0
T22	0	1037	0	0
T40	0	6408	0	0
T69	0	4	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T6,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	441869811	441782382	0	0
CheckNGreaterZero_A	954	954	0	0
GntImpliesReady_A	441869811	2239977	0	0
GntImpliesValid_A	441869811	2239977	0	0
GrantKnown_A	441869811	441782382	0	0
IdxKnown_A	441869811	441782382	0	0
IndexIsCorrect_A	441869811	2239977	0	0
LockArbDecision_A	441869811	0	0	0
NoReadyValidNoGrant_A	441869811	0	0	0
ReadyAndValidImplyGrant_A	441869811	2239977	0	0
ReqAndReadyImplyGrant_A	441869811	2239977	0	0
ReqImpliesValid_A	441869811	2239977	0	0
ReqStaysHighUntilGranted0_M	441869811	0	0	0
RoundRobin_A	441869811	4	0	954
ValidKnown_A	441869811	441782382	0	0
gen_data_port_assertion.DataFlow_A	441869811	2239977	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441869811	441782382	0	0
T1	60528	60428	0	0
T2	184693	184685	0	0
T3	15354	15271	0	0
T4	346651	346586	0	0
T5	607261	607202	0	0
T6	221020	221012	0	0
T7	357917	357912	0	0
T8	270827	270775	0	0
T9	86452	86398	0	0
T10	44834	44763	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441869811	2239977	0	0
T1	60528	832	0	0
T2	184693	7727	0	0
T3	15354	832	0	0
T4	346651	0	0	0
T5	607261	832	0	0
T6	221020	11397	0	0
T7	357917	9238	0	0
T8	270827	832	0	0
T9	86452	832	0	0
T10	44834	964	0	0
T11	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441869811	2239977	0	0
T1	60528	832	0	0
T2	184693	7727	0	0
T3	15354	832	0	0
T4	346651	0	0	0
T5	607261	832	0	0
T6	221020	11397	0	0
T7	357917	9238	0	0
T8	270827	832	0	0
T9	86452	832	0	0
T10	44834	964	0	0
T11	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441869811	441782382	0	0
T1	60528	60428	0	0
T2	184693	184685	0	0
T3	15354	15271	0	0
T4	346651	346586	0	0
T5	607261	607202	0	0
T6	221020	221012	0	0
T7	357917	357912	0	0
T8	270827	270775	0	0
T9	86452	86398	0	0
T10	44834	44763	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441869811	441782382	0	0
T1	60528	60428	0	0
T2	184693	184685	0	0
T3	15354	15271	0	0
T4	346651	346586	0	0
T5	607261	607202	0	0
T6	221020	221012	0	0
T7	357917	357912	0	0
T8	270827	270775	0	0
T9	86452	86398	0	0
T10	44834	44763	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441869811	2239977	0	0
T1	60528	832	0	0
T2	184693	7727	0	0
T3	15354	832	0	0
T4	346651	0	0	0
T5	607261	832	0	0
T6	221020	11397	0	0
T7	357917	9238	0	0
T8	270827	832	0	0
T9	86452	832	0	0
T10	44834	964	0	0
T11	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441869811	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441869811	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441869811	2239977	0	0
T1	60528	832	0	0
T2	184693	7727	0	0
T3	15354	832	0	0
T4	346651	0	0	0
T5	607261	832	0	0
T6	221020	11397	0	0
T7	357917	9238	0	0
T8	270827	832	0	0
T9	86452	832	0	0
T10	44834	964	0	0
T11	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441869811	2239977	0	0
T1	60528	832	0	0
T2	184693	7727	0	0
T3	15354	832	0	0
T4	346651	0	0	0
T5	607261	832	0	0
T6	221020	11397	0	0
T7	357917	9238	0	0
T8	270827	832	0	0
T9	86452	832	0	0
T10	44834	964	0	0
T11	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441869811	2239977	0	0
T1	60528	832	0	0
T2	184693	7727	0	0
T3	15354	832	0	0
T4	346651	0	0	0
T5	607261	832	0	0
T6	221020	11397	0	0
T7	357917	9238	0	0
T8	270827	832	0	0
T9	86452	832	0	0
T10	44834	964	0	0
T11	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	441869811	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441869811	4	0	954
T56	170956	1	0	1
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	172891	0	0	1
T61	541440	0	0	1
T62	123708	0	0	1
T63	465193	0	0	1
T64	227401	0	0	1
T65	234220	0	0	1
T66	1853	0	0	1
T67	6787	0	0	1
T68	954	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441869811	441782382	0	0
T1	60528	60428	0	0
T2	184693	184685	0	0
T3	15354	15271	0	0
T4	346651	346586	0	0
T5	607261	607202	0	0
T6	221020	221012	0	0
T7	357917	357912	0	0
T8	270827	270775	0	0
T9	86452	86398	0	0
T10	44834	44763	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441869811	2239977	0	0
T1	60528	832	0	0
T2	184693	7727	0	0
T3	15354	832	0	0
T4	346651	0	0	0
T5	607261	832	0	0
T6	221020	11397	0	0
T7	357917	9238	0	0
T8	270827	832	0	0
T9	86452	832	0	0
T10	44834	964	0	0
T11	0	832	0	0