Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
3045 |
0 |
0 |
T73 |
52682 |
1 |
0 |
0 |
T74 |
5069 |
12 |
0 |
0 |
T75 |
3983 |
6 |
0 |
0 |
T105 |
5969 |
167 |
0 |
0 |
T106 |
102032 |
6 |
0 |
0 |
T107 |
18588 |
3 |
0 |
0 |
T108 |
6838 |
256 |
0 |
0 |
T109 |
9247 |
4 |
0 |
0 |
T117 |
5519 |
18 |
0 |
0 |
T123 |
18686 |
7 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
1312 |
0 |
0 |
T106 |
102032 |
127 |
0 |
0 |
T115 |
15509 |
22 |
0 |
0 |
T122 |
31893 |
35 |
0 |
0 |
T125 |
35381 |
42 |
0 |
0 |
T126 |
7194 |
7 |
0 |
0 |
T129 |
4138 |
7 |
0 |
0 |
T137 |
234484 |
425 |
0 |
0 |
T161 |
12744 |
14 |
0 |
0 |
T171 |
71319 |
71 |
0 |
0 |
T172 |
13290 |
15 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
1250 |
0 |
0 |
T106 |
102032 |
104 |
0 |
0 |
T115 |
15509 |
23 |
0 |
0 |
T122 |
31893 |
23 |
0 |
0 |
T125 |
35381 |
47 |
0 |
0 |
T126 |
7194 |
7 |
0 |
0 |
T131 |
3481 |
1 |
0 |
0 |
T137 |
234484 |
341 |
0 |
0 |
T161 |
12744 |
40 |
0 |
0 |
T171 |
71319 |
87 |
0 |
0 |
T172 |
13290 |
56 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
1893 |
0 |
0 |
T106 |
102032 |
255 |
0 |
0 |
T115 |
15509 |
12 |
0 |
0 |
T122 |
31893 |
77 |
0 |
0 |
T125 |
35381 |
72 |
0 |
0 |
T126 |
7194 |
5 |
0 |
0 |
T129 |
4138 |
5 |
0 |
0 |
T131 |
3481 |
11 |
0 |
0 |
T137 |
234484 |
462 |
0 |
0 |
T161 |
12744 |
55 |
0 |
0 |
T171 |
71319 |
154 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
10599 |
0 |
0 |
T106 |
102032 |
2217 |
0 |
0 |
T115 |
15509 |
171 |
0 |
0 |
T122 |
31893 |
576 |
0 |
0 |
T125 |
35381 |
389 |
0 |
0 |
T126 |
7194 |
215 |
0 |
0 |
T129 |
4138 |
2 |
0 |
0 |
T137 |
234484 |
407 |
0 |
0 |
T161 |
12744 |
37 |
0 |
0 |
T171 |
71319 |
1057 |
0 |
0 |
T172 |
13290 |
59 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
11575 |
0 |
0 |
T106 |
102032 |
2668 |
0 |
0 |
T115 |
15509 |
256 |
0 |
0 |
T122 |
31893 |
574 |
0 |
0 |
T125 |
35381 |
249 |
0 |
0 |
T126 |
7194 |
129 |
0 |
0 |
T129 |
4138 |
75 |
0 |
0 |
T137 |
234484 |
376 |
0 |
0 |
T161 |
12744 |
60 |
0 |
0 |
T171 |
71319 |
1084 |
0 |
0 |
T172 |
13290 |
101 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
10946 |
0 |
0 |
T106 |
102032 |
2001 |
0 |
0 |
T110 |
13279 |
2 |
0 |
0 |
T115 |
15509 |
138 |
0 |
0 |
T122 |
31893 |
478 |
0 |
0 |
T125 |
35381 |
577 |
0 |
0 |
T126 |
7194 |
164 |
0 |
0 |
T129 |
4138 |
46 |
0 |
0 |
T131 |
3481 |
76 |
0 |
0 |
T161 |
12744 |
5 |
0 |
0 |
T171 |
71319 |
1013 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
11390 |
0 |
0 |
T106 |
102032 |
2209 |
0 |
0 |
T115 |
15509 |
140 |
0 |
0 |
T122 |
31893 |
634 |
0 |
0 |
T125 |
35381 |
544 |
0 |
0 |
T126 |
7194 |
141 |
0 |
0 |
T129 |
4138 |
71 |
0 |
0 |
T137 |
234484 |
444 |
0 |
0 |
T161 |
12744 |
43 |
0 |
0 |
T171 |
71319 |
1369 |
0 |
0 |
T172 |
13290 |
18 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
12803 |
0 |
0 |
T106 |
102032 |
2646 |
0 |
0 |
T115 |
15509 |
224 |
0 |
0 |
T122 |
31893 |
576 |
0 |
0 |
T125 |
35381 |
592 |
0 |
0 |
T126 |
7194 |
148 |
0 |
0 |
T137 |
234484 |
416 |
0 |
0 |
T161 |
12744 |
29 |
0 |
0 |
T171 |
71319 |
1400 |
0 |
0 |
T172 |
13290 |
43 |
0 |
0 |
T173 |
72759 |
1590 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
10468 |
0 |
0 |
T106 |
102032 |
1907 |
0 |
0 |
T115 |
15509 |
221 |
0 |
0 |
T122 |
31893 |
411 |
0 |
0 |
T125 |
35381 |
1023 |
0 |
0 |
T126 |
7194 |
12 |
0 |
0 |
T131 |
3481 |
57 |
0 |
0 |
T137 |
234484 |
336 |
0 |
0 |
T161 |
12744 |
60 |
0 |
0 |
T171 |
71319 |
1124 |
0 |
0 |
T172 |
13290 |
22 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
11867 |
0 |
0 |
T106 |
102032 |
1644 |
0 |
0 |
T115 |
15509 |
365 |
0 |
0 |
T122 |
31893 |
716 |
0 |
0 |
T125 |
35381 |
658 |
0 |
0 |
T126 |
7194 |
121 |
0 |
0 |
T129 |
4138 |
55 |
0 |
0 |
T131 |
3481 |
78 |
0 |
0 |
T137 |
234484 |
377 |
0 |
0 |
T161 |
12744 |
59 |
0 |
0 |
T171 |
71319 |
1234 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
10226 |
0 |
0 |
T106 |
102032 |
1524 |
0 |
0 |
T115 |
15509 |
118 |
0 |
0 |
T122 |
31893 |
609 |
0 |
0 |
T125 |
35381 |
385 |
0 |
0 |
T126 |
7194 |
143 |
0 |
0 |
T129 |
4138 |
89 |
0 |
0 |
T131 |
3481 |
96 |
0 |
0 |
T137 |
234484 |
363 |
0 |
0 |
T161 |
12744 |
54 |
0 |
0 |
T171 |
71319 |
1009 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
5144 |
0 |
0 |
T106 |
102032 |
571 |
0 |
0 |
T115 |
15509 |
110 |
0 |
0 |
T122 |
31893 |
319 |
0 |
0 |
T125 |
35381 |
252 |
0 |
0 |
T126 |
7194 |
11 |
0 |
0 |
T129 |
4138 |
1 |
0 |
0 |
T131 |
3481 |
28 |
0 |
0 |
T137 |
234484 |
448 |
0 |
0 |
T161 |
12744 |
74 |
0 |
0 |
T171 |
71319 |
538 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
5401 |
0 |
0 |
T106 |
102032 |
675 |
0 |
0 |
T115 |
15509 |
160 |
0 |
0 |
T122 |
31893 |
211 |
0 |
0 |
T125 |
35381 |
349 |
0 |
0 |
T126 |
7194 |
3 |
0 |
0 |
T129 |
4138 |
37 |
0 |
0 |
T131 |
3481 |
32 |
0 |
0 |
T137 |
234484 |
419 |
0 |
0 |
T161 |
12744 |
33 |
0 |
0 |
T171 |
71319 |
483 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
5120 |
0 |
0 |
T106 |
102032 |
792 |
0 |
0 |
T115 |
15509 |
64 |
0 |
0 |
T122 |
31893 |
136 |
0 |
0 |
T125 |
35381 |
215 |
0 |
0 |
T126 |
7194 |
47 |
0 |
0 |
T129 |
4138 |
6 |
0 |
0 |
T131 |
3481 |
1 |
0 |
0 |
T137 |
234484 |
473 |
0 |
0 |
T161 |
12744 |
15 |
0 |
0 |
T171 |
71319 |
588 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
5053 |
0 |
0 |
T106 |
102032 |
592 |
0 |
0 |
T115 |
15509 |
109 |
0 |
0 |
T122 |
31893 |
323 |
0 |
0 |
T125 |
35381 |
220 |
0 |
0 |
T126 |
7194 |
63 |
0 |
0 |
T129 |
4138 |
1 |
0 |
0 |
T131 |
3481 |
4 |
0 |
0 |
T137 |
234484 |
431 |
0 |
0 |
T161 |
12744 |
29 |
0 |
0 |
T171 |
71319 |
493 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
5098 |
0 |
0 |
T106 |
102032 |
813 |
0 |
0 |
T115 |
15509 |
61 |
0 |
0 |
T122 |
31893 |
253 |
0 |
0 |
T125 |
35381 |
238 |
0 |
0 |
T126 |
7194 |
56 |
0 |
0 |
T131 |
3481 |
26 |
0 |
0 |
T137 |
234484 |
480 |
0 |
0 |
T161 |
12744 |
67 |
0 |
0 |
T171 |
71319 |
552 |
0 |
0 |
T172 |
13290 |
1 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
5345 |
0 |
0 |
T106 |
102032 |
951 |
0 |
0 |
T115 |
15509 |
62 |
0 |
0 |
T122 |
31893 |
224 |
0 |
0 |
T125 |
35381 |
355 |
0 |
0 |
T126 |
7194 |
106 |
0 |
0 |
T137 |
234484 |
382 |
0 |
0 |
T161 |
12744 |
16 |
0 |
0 |
T171 |
71319 |
587 |
0 |
0 |
T172 |
13290 |
12 |
0 |
0 |
T173 |
72759 |
639 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
5444 |
0 |
0 |
T106 |
102032 |
766 |
0 |
0 |
T115 |
15509 |
111 |
0 |
0 |
T122 |
31893 |
340 |
0 |
0 |
T125 |
35381 |
243 |
0 |
0 |
T126 |
7194 |
47 |
0 |
0 |
T129 |
4138 |
10 |
0 |
0 |
T137 |
234484 |
390 |
0 |
0 |
T161 |
12744 |
40 |
0 |
0 |
T171 |
71319 |
630 |
0 |
0 |
T172 |
13290 |
87 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
5440 |
0 |
0 |
T106 |
102032 |
831 |
0 |
0 |
T115 |
15509 |
21 |
0 |
0 |
T122 |
31893 |
126 |
0 |
0 |
T125 |
35381 |
355 |
0 |
0 |
T126 |
7194 |
8 |
0 |
0 |
T129 |
4138 |
18 |
0 |
0 |
T131 |
3481 |
5 |
0 |
0 |
T137 |
234484 |
444 |
0 |
0 |
T161 |
12744 |
39 |
0 |
0 |
T171 |
71319 |
649 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
5166 |
0 |
0 |
T106 |
102032 |
800 |
0 |
0 |
T115 |
15509 |
85 |
0 |
0 |
T122 |
31893 |
319 |
0 |
0 |
T125 |
35381 |
314 |
0 |
0 |
T126 |
7194 |
3 |
0 |
0 |
T131 |
3481 |
41 |
0 |
0 |
T137 |
234484 |
408 |
0 |
0 |
T161 |
12744 |
37 |
0 |
0 |
T171 |
71319 |
487 |
0 |
0 |
T172 |
13290 |
48 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
4957 |
0 |
0 |
T106 |
102032 |
743 |
0 |
0 |
T115 |
15509 |
64 |
0 |
0 |
T122 |
31893 |
235 |
0 |
0 |
T125 |
35381 |
332 |
0 |
0 |
T126 |
7194 |
66 |
0 |
0 |
T129 |
4138 |
11 |
0 |
0 |
T131 |
3481 |
3 |
0 |
0 |
T137 |
234484 |
461 |
0 |
0 |
T161 |
12744 |
65 |
0 |
0 |
T171 |
71319 |
436 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
4933 |
0 |
0 |
T106 |
102032 |
843 |
0 |
0 |
T115 |
15509 |
188 |
0 |
0 |
T122 |
31893 |
209 |
0 |
0 |
T125 |
35381 |
259 |
0 |
0 |
T126 |
7194 |
4 |
0 |
0 |
T129 |
4138 |
19 |
0 |
0 |
T131 |
3481 |
1 |
0 |
0 |
T137 |
234484 |
407 |
0 |
0 |
T161 |
12744 |
74 |
0 |
0 |
T171 |
71319 |
543 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
5137 |
0 |
0 |
T106 |
102032 |
750 |
0 |
0 |
T115 |
15509 |
128 |
0 |
0 |
T122 |
31893 |
173 |
0 |
0 |
T125 |
35381 |
272 |
0 |
0 |
T126 |
7194 |
48 |
0 |
0 |
T131 |
3481 |
4 |
0 |
0 |
T137 |
234484 |
407 |
0 |
0 |
T161 |
12744 |
38 |
0 |
0 |
T171 |
71319 |
754 |
0 |
0 |
T172 |
13290 |
50 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
5455 |
0 |
0 |
T106 |
102032 |
849 |
0 |
0 |
T115 |
15509 |
66 |
0 |
0 |
T122 |
31893 |
217 |
0 |
0 |
T125 |
35381 |
200 |
0 |
0 |
T126 |
7194 |
96 |
0 |
0 |
T129 |
4138 |
28 |
0 |
0 |
T131 |
3481 |
1 |
0 |
0 |
T137 |
234484 |
376 |
0 |
0 |
T161 |
12744 |
36 |
0 |
0 |
T171 |
71319 |
556 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
5556 |
0 |
0 |
T106 |
102032 |
684 |
0 |
0 |
T115 |
15509 |
73 |
0 |
0 |
T122 |
31893 |
333 |
0 |
0 |
T125 |
35381 |
440 |
0 |
0 |
T126 |
7194 |
43 |
0 |
0 |
T137 |
234484 |
436 |
0 |
0 |
T161 |
12744 |
44 |
0 |
0 |
T171 |
71319 |
488 |
0 |
0 |
T172 |
13290 |
59 |
0 |
0 |
T173 |
72759 |
649 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
4879 |
0 |
0 |
T106 |
102032 |
876 |
0 |
0 |
T115 |
15509 |
50 |
0 |
0 |
T122 |
31893 |
278 |
0 |
0 |
T125 |
35381 |
168 |
0 |
0 |
T126 |
7194 |
9 |
0 |
0 |
T129 |
4138 |
3 |
0 |
0 |
T131 |
3481 |
9 |
0 |
0 |
T137 |
234484 |
399 |
0 |
0 |
T161 |
12744 |
67 |
0 |
0 |
T171 |
71319 |
451 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
4785 |
0 |
0 |
T106 |
102032 |
679 |
0 |
0 |
T115 |
15509 |
28 |
0 |
0 |
T122 |
31893 |
162 |
0 |
0 |
T125 |
35381 |
269 |
0 |
0 |
T126 |
7194 |
9 |
0 |
0 |
T129 |
4138 |
5 |
0 |
0 |
T137 |
234484 |
375 |
0 |
0 |
T161 |
12744 |
33 |
0 |
0 |
T171 |
71319 |
470 |
0 |
0 |
T172 |
13290 |
101 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
5581 |
0 |
0 |
T106 |
102032 |
939 |
0 |
0 |
T110 |
13279 |
6 |
0 |
0 |
T115 |
15509 |
102 |
0 |
0 |
T122 |
31893 |
411 |
0 |
0 |
T125 |
35381 |
258 |
0 |
0 |
T126 |
7194 |
5 |
0 |
0 |
T129 |
4138 |
23 |
0 |
0 |
T137 |
234484 |
403 |
0 |
0 |
T161 |
12744 |
36 |
0 |
0 |
T171 |
71319 |
554 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
5506 |
0 |
0 |
T106 |
102032 |
1007 |
0 |
0 |
T115 |
15509 |
127 |
0 |
0 |
T122 |
31893 |
198 |
0 |
0 |
T125 |
35381 |
195 |
0 |
0 |
T126 |
7194 |
56 |
0 |
0 |
T129 |
4138 |
29 |
0 |
0 |
T131 |
3481 |
26 |
0 |
0 |
T137 |
234484 |
380 |
0 |
0 |
T161 |
12744 |
46 |
0 |
0 |
T171 |
71319 |
559 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
5647 |
0 |
0 |
T106 |
102032 |
910 |
0 |
0 |
T115 |
15509 |
78 |
0 |
0 |
T122 |
31893 |
188 |
0 |
0 |
T125 |
35381 |
341 |
0 |
0 |
T126 |
7194 |
115 |
0 |
0 |
T129 |
4138 |
24 |
0 |
0 |
T137 |
234484 |
411 |
0 |
0 |
T161 |
12744 |
9 |
0 |
0 |
T171 |
71319 |
750 |
0 |
0 |
T172 |
13290 |
48 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
5192 |
0 |
0 |
T106 |
102032 |
712 |
0 |
0 |
T115 |
15509 |
127 |
0 |
0 |
T122 |
31893 |
344 |
0 |
0 |
T125 |
35381 |
223 |
0 |
0 |
T126 |
7194 |
110 |
0 |
0 |
T129 |
4138 |
7 |
0 |
0 |
T131 |
3481 |
25 |
0 |
0 |
T137 |
234484 |
408 |
0 |
0 |
T161 |
12744 |
32 |
0 |
0 |
T171 |
71319 |
605 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
5027 |
0 |
0 |
T106 |
102032 |
759 |
0 |
0 |
T115 |
15509 |
100 |
0 |
0 |
T122 |
31893 |
240 |
0 |
0 |
T125 |
35381 |
251 |
0 |
0 |
T126 |
7194 |
111 |
0 |
0 |
T129 |
4138 |
33 |
0 |
0 |
T137 |
234484 |
462 |
0 |
0 |
T161 |
12744 |
50 |
0 |
0 |
T171 |
71319 |
532 |
0 |
0 |
T172 |
13290 |
7 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
4451 |
0 |
0 |
T106 |
102032 |
748 |
0 |
0 |
T115 |
15509 |
62 |
0 |
0 |
T122 |
31893 |
85 |
0 |
0 |
T125 |
35381 |
266 |
0 |
0 |
T126 |
7194 |
108 |
0 |
0 |
T129 |
4138 |
31 |
0 |
0 |
T131 |
3481 |
27 |
0 |
0 |
T137 |
234484 |
382 |
0 |
0 |
T161 |
12744 |
33 |
0 |
0 |
T171 |
71319 |
508 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
5646 |
0 |
0 |
T106 |
102032 |
1125 |
0 |
0 |
T115 |
15509 |
108 |
0 |
0 |
T122 |
31893 |
245 |
0 |
0 |
T125 |
35381 |
247 |
0 |
0 |
T126 |
7194 |
56 |
0 |
0 |
T129 |
4138 |
31 |
0 |
0 |
T131 |
3481 |
43 |
0 |
0 |
T137 |
234484 |
416 |
0 |
0 |
T161 |
12744 |
20 |
0 |
0 |
T171 |
71319 |
610 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
5669 |
0 |
0 |
T106 |
102032 |
952 |
0 |
0 |
T115 |
15509 |
143 |
0 |
0 |
T122 |
31893 |
232 |
0 |
0 |
T125 |
35381 |
360 |
0 |
0 |
T126 |
7194 |
52 |
0 |
0 |
T129 |
4138 |
37 |
0 |
0 |
T131 |
3481 |
32 |
0 |
0 |
T137 |
234484 |
419 |
0 |
0 |
T161 |
12744 |
25 |
0 |
0 |
T171 |
71319 |
603 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
1647 |
0 |
0 |
T106 |
102032 |
140 |
0 |
0 |
T115 |
15509 |
25 |
0 |
0 |
T122 |
31893 |
67 |
0 |
0 |
T125 |
35381 |
53 |
0 |
0 |
T126 |
7194 |
13 |
0 |
0 |
T137 |
234484 |
415 |
0 |
0 |
T161 |
12744 |
66 |
0 |
0 |
T171 |
71319 |
109 |
0 |
0 |
T172 |
13290 |
58 |
0 |
0 |
T173 |
72759 |
122 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
1483 |
0 |
0 |
T106 |
102032 |
155 |
0 |
0 |
T115 |
15509 |
32 |
0 |
0 |
T122 |
31893 |
54 |
0 |
0 |
T125 |
35381 |
60 |
0 |
0 |
T126 |
7194 |
3 |
0 |
0 |
T131 |
3481 |
2 |
0 |
0 |
T137 |
234484 |
402 |
0 |
0 |
T161 |
12744 |
25 |
0 |
0 |
T171 |
71319 |
110 |
0 |
0 |
T172 |
13290 |
9 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
1491 |
0 |
0 |
T106 |
102032 |
151 |
0 |
0 |
T115 |
15509 |
15 |
0 |
0 |
T122 |
31893 |
68 |
0 |
0 |
T125 |
35381 |
44 |
0 |
0 |
T126 |
7194 |
21 |
0 |
0 |
T137 |
234484 |
409 |
0 |
0 |
T161 |
12744 |
46 |
0 |
0 |
T171 |
71319 |
92 |
0 |
0 |
T172 |
13290 |
47 |
0 |
0 |
T173 |
72759 |
124 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
1732 |
0 |
0 |
T106 |
102032 |
157 |
0 |
0 |
T115 |
15509 |
43 |
0 |
0 |
T122 |
31893 |
51 |
0 |
0 |
T125 |
35381 |
47 |
0 |
0 |
T126 |
7194 |
12 |
0 |
0 |
T131 |
3481 |
5 |
0 |
0 |
T137 |
234484 |
424 |
0 |
0 |
T161 |
12744 |
62 |
0 |
0 |
T171 |
71319 |
92 |
0 |
0 |
T172 |
13290 |
83 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
2404 |
0 |
0 |
T106 |
102032 |
365 |
0 |
0 |
T115 |
15509 |
41 |
0 |
0 |
T122 |
31893 |
44 |
0 |
0 |
T125 |
35381 |
160 |
0 |
0 |
T126 |
7194 |
25 |
0 |
0 |
T129 |
4138 |
2 |
0 |
0 |
T131 |
3481 |
1 |
0 |
0 |
T137 |
234484 |
436 |
0 |
0 |
T161 |
12744 |
32 |
0 |
0 |
T171 |
71319 |
183 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
4289 |
0 |
0 |
T12 |
820185 |
68 |
0 |
0 |
T14 |
0 |
21 |
0 |
0 |
T18 |
0 |
39 |
0 |
0 |
T20 |
0 |
2 |
0 |
0 |
T22 |
100130 |
0 |
0 |
0 |
T23 |
198148 |
0 |
0 |
0 |
T24 |
11840 |
0 |
0 |
0 |
T25 |
629284 |
0 |
0 |
0 |
T26 |
1779 |
0 |
0 |
0 |
T27 |
1531 |
0 |
0 |
0 |
T28 |
7352 |
0 |
0 |
0 |
T29 |
963 |
0 |
0 |
0 |
T30 |
1369 |
0 |
0 |
0 |
T174 |
0 |
27 |
0 |
0 |
T175 |
0 |
17 |
0 |
0 |
T176 |
0 |
33 |
0 |
0 |
T177 |
0 |
42 |
0 |
0 |
T178 |
0 |
44 |
0 |
0 |
T179 |
0 |
31 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
1671 |
0 |
0 |
T106 |
102032 |
169 |
0 |
0 |
T115 |
15509 |
29 |
0 |
0 |
T122 |
31893 |
53 |
0 |
0 |
T125 |
35381 |
54 |
0 |
0 |
T126 |
7194 |
9 |
0 |
0 |
T129 |
4138 |
2 |
0 |
0 |
T131 |
3481 |
6 |
0 |
0 |
T137 |
234484 |
458 |
0 |
0 |
T161 |
12744 |
43 |
0 |
0 |
T171 |
71319 |
124 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
1477 |
0 |
0 |
T106 |
102032 |
139 |
0 |
0 |
T115 |
15509 |
30 |
0 |
0 |
T122 |
31893 |
55 |
0 |
0 |
T125 |
35381 |
57 |
0 |
0 |
T126 |
7194 |
14 |
0 |
0 |
T137 |
234484 |
356 |
0 |
0 |
T161 |
12744 |
38 |
0 |
0 |
T171 |
71319 |
87 |
0 |
0 |
T172 |
13290 |
47 |
0 |
0 |
T173 |
72759 |
103 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
1289 |
0 |
0 |
T106 |
102032 |
105 |
0 |
0 |
T115 |
15509 |
21 |
0 |
0 |
T122 |
31893 |
30 |
0 |
0 |
T125 |
35381 |
43 |
0 |
0 |
T126 |
7194 |
3 |
0 |
0 |
T129 |
4138 |
4 |
0 |
0 |
T137 |
234484 |
454 |
0 |
0 |
T161 |
12744 |
22 |
0 |
0 |
T171 |
71319 |
74 |
0 |
0 |
T172 |
13290 |
43 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
1275 |
0 |
0 |
T106 |
102032 |
125 |
0 |
0 |
T115 |
15509 |
25 |
0 |
0 |
T122 |
31893 |
24 |
0 |
0 |
T125 |
35381 |
28 |
0 |
0 |
T126 |
7194 |
7 |
0 |
0 |
T131 |
3481 |
4 |
0 |
0 |
T137 |
234484 |
397 |
0 |
0 |
T161 |
12744 |
50 |
0 |
0 |
T171 |
71319 |
78 |
0 |
0 |
T172 |
13290 |
99 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
1302 |
0 |
0 |
T106 |
102032 |
153 |
0 |
0 |
T115 |
15509 |
25 |
0 |
0 |
T122 |
31893 |
31 |
0 |
0 |
T125 |
35381 |
49 |
0 |
0 |
T126 |
7194 |
10 |
0 |
0 |
T129 |
4138 |
6 |
0 |
0 |
T131 |
3481 |
7 |
0 |
0 |
T137 |
234484 |
358 |
0 |
0 |
T161 |
12744 |
73 |
0 |
0 |
T171 |
71319 |
81 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
1257 |
0 |
0 |
T106 |
102032 |
105 |
0 |
0 |
T115 |
15509 |
17 |
0 |
0 |
T122 |
31893 |
48 |
0 |
0 |
T125 |
35381 |
41 |
0 |
0 |
T126 |
7194 |
9 |
0 |
0 |
T137 |
234484 |
356 |
0 |
0 |
T161 |
12744 |
74 |
0 |
0 |
T171 |
71319 |
63 |
0 |
0 |
T172 |
13290 |
93 |
0 |
0 |
T173 |
72759 |
59 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
2299 |
0 |
0 |
T106 |
102032 |
291 |
0 |
0 |
T115 |
15509 |
48 |
0 |
0 |
T122 |
31893 |
117 |
0 |
0 |
T125 |
35381 |
118 |
0 |
0 |
T126 |
7194 |
12 |
0 |
0 |
T129 |
4138 |
2 |
0 |
0 |
T131 |
3481 |
9 |
0 |
0 |
T137 |
234484 |
431 |
0 |
0 |
T161 |
12744 |
43 |
0 |
0 |
T171 |
71319 |
194 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
1271 |
0 |
0 |
T106 |
102032 |
104 |
0 |
0 |
T115 |
15509 |
23 |
0 |
0 |
T122 |
31893 |
38 |
0 |
0 |
T125 |
35381 |
29 |
0 |
0 |
T126 |
7194 |
12 |
0 |
0 |
T137 |
234484 |
390 |
0 |
0 |
T161 |
12744 |
36 |
0 |
0 |
T171 |
71319 |
76 |
0 |
0 |
T172 |
13290 |
19 |
0 |
0 |
T173 |
72759 |
84 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
2411 |
0 |
0 |
T106 |
102032 |
286 |
0 |
0 |
T115 |
15509 |
40 |
0 |
0 |
T122 |
31893 |
51 |
0 |
0 |
T125 |
35381 |
96 |
0 |
0 |
T126 |
7194 |
29 |
0 |
0 |
T129 |
4138 |
10 |
0 |
0 |
T131 |
3481 |
14 |
0 |
0 |
T137 |
234484 |
410 |
0 |
0 |
T161 |
12744 |
33 |
0 |
0 |
T171 |
71319 |
185 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
1592 |
0 |
0 |
T106 |
102032 |
167 |
0 |
0 |
T115 |
15509 |
32 |
0 |
0 |
T122 |
31893 |
42 |
0 |
0 |
T125 |
35381 |
41 |
0 |
0 |
T126 |
7194 |
18 |
0 |
0 |
T129 |
4138 |
1 |
0 |
0 |
T131 |
3481 |
7 |
0 |
0 |
T137 |
234484 |
369 |
0 |
0 |
T161 |
12744 |
64 |
0 |
0 |
T171 |
71319 |
119 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
1221 |
0 |
0 |
T106 |
102032 |
78 |
0 |
0 |
T115 |
15509 |
18 |
0 |
0 |
T122 |
31893 |
25 |
0 |
0 |
T125 |
35381 |
39 |
0 |
0 |
T126 |
7194 |
1 |
0 |
0 |
T137 |
234484 |
384 |
0 |
0 |
T161 |
12744 |
35 |
0 |
0 |
T171 |
71319 |
74 |
0 |
0 |
T172 |
13290 |
58 |
0 |
0 |
T173 |
72759 |
65 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
1177 |
0 |
0 |
T106 |
102032 |
102 |
0 |
0 |
T115 |
15509 |
19 |
0 |
0 |
T122 |
31893 |
25 |
0 |
0 |
T125 |
35381 |
31 |
0 |
0 |
T126 |
7194 |
14 |
0 |
0 |
T131 |
3481 |
1 |
0 |
0 |
T137 |
234484 |
381 |
0 |
0 |
T161 |
12744 |
54 |
0 |
0 |
T171 |
71319 |
91 |
0 |
0 |
T172 |
13290 |
47 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
1224 |
0 |
0 |
T106 |
102032 |
151 |
0 |
0 |
T115 |
15509 |
13 |
0 |
0 |
T122 |
31893 |
43 |
0 |
0 |
T125 |
35381 |
36 |
0 |
0 |
T126 |
7194 |
12 |
0 |
0 |
T129 |
4138 |
1 |
0 |
0 |
T137 |
234484 |
320 |
0 |
0 |
T161 |
12744 |
20 |
0 |
0 |
T171 |
71319 |
60 |
0 |
0 |
T172 |
13290 |
80 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
1338 |
0 |
0 |
T106 |
102032 |
119 |
0 |
0 |
T115 |
15509 |
27 |
0 |
0 |
T122 |
31893 |
46 |
0 |
0 |
T125 |
35381 |
54 |
0 |
0 |
T126 |
7194 |
2 |
0 |
0 |
T129 |
4138 |
7 |
0 |
0 |
T137 |
234484 |
410 |
0 |
0 |
T161 |
12744 |
61 |
0 |
0 |
T171 |
71319 |
77 |
0 |
0 |
T172 |
13290 |
35 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
1301 |
0 |
0 |
T106 |
102032 |
107 |
0 |
0 |
T115 |
15509 |
16 |
0 |
0 |
T122 |
31893 |
27 |
0 |
0 |
T125 |
35381 |
30 |
0 |
0 |
T126 |
7194 |
6 |
0 |
0 |
T137 |
234484 |
367 |
0 |
0 |
T161 |
12744 |
70 |
0 |
0 |
T171 |
71319 |
67 |
0 |
0 |
T172 |
13290 |
70 |
0 |
0 |
T173 |
72759 |
64 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
444285511 |
1363 |
0 |
0 |
T106 |
102032 |
127 |
0 |
0 |
T115 |
15509 |
14 |
0 |
0 |
T122 |
31893 |
31 |
0 |
0 |
T125 |
35381 |
35 |
0 |
0 |
T126 |
7194 |
11 |
0 |
0 |
T129 |
4138 |
6 |
0 |
0 |
T137 |
234484 |
476 |
0 |
0 |
T161 |
12744 |
44 |
0 |
0 |
T171 |
71319 |
82 |
0 |
0 |
T172 |
13290 |
45 |
0 |
0 |