Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3240458	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4048843

1

T1

47152

T2

980

T3

891

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4009866	1			T1	92343		T2	205		T3	35
values[0x0]	1639167	1			T1	458		T2	426		T3	454
values[0x1]	1640268	1			T1	471		T2	465		T3	426

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2313261	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4976040

1

T1

56434

T2

1002

T3

894

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26878	1			T1	338		T5	38		T9	3
valid_sources[0x01]	28382	1			T1	363		T5	25		T9	5
valid_sources[0x02]	28403	1			T1	382		T5	27		T9	8
valid_sources[0x03]	26273	1			T1	376		T5	39		T9	10
valid_sources[0x04]	28064	1			T1	347		T5	36		T9	6
valid_sources[0x05]	27074	1			T1	361		T5	46		T7	1
valid_sources[0x06]	24944	1			T1	397		T5	33		T9	2
valid_sources[0x07]	27519	1			T1	367		T3	427		T5	45
valid_sources[0x08]	31980	1			T1	388		T5	25		T9	5
valid_sources[0x09]	43671	1			T1	426		T5	35		T9	7
valid_sources[0x0a]	34780	1			T1	399		T5	36		T9	3
valid_sources[0x0b]	30298	1			T1	325		T5	30		T9	6
valid_sources[0x0c]	26512	1			T1	323		T5	16		T9	4
valid_sources[0x0d]	27463	1			T1	377		T5	28		T10	8
valid_sources[0x0e]	25841	1			T1	373		T5	40		T9	6
valid_sources[0x0f]	26219	1			T1	365		T5	37		T9	9
valid_sources[0x10]	25721	1			T1	373		T4	1		T5	36
valid_sources[0x11]	28844	1			T1	387		T5	33		T9	7
valid_sources[0x12]	26705	1			T1	357		T5	37		T9	7
valid_sources[0x13]	26834	1			T1	357		T5	32		T9	6
valid_sources[0x14]	27598	1			T1	363		T5	31		T9	4
valid_sources[0x15]	26554	1			T1	336		T5	27		T9	3
valid_sources[0x16]	28190	1			T1	380		T4	2		T5	36
valid_sources[0x17]	26317	1			T1	373		T4	2		T5	31
valid_sources[0x18]	31278	1			T1	366		T5	28		T9	2
valid_sources[0x19]	28584	1			T1	356		T5	38		T9	4
valid_sources[0x1a]	26792	1			T1	371		T5	35		T9	8
valid_sources[0x1b]	26009	1			T1	349		T5	56		T9	3
valid_sources[0x1c]	28942	1			T1	363		T4	2		T5	34
valid_sources[0x1d]	29832	1			T1	313		T5	32		T9	6
valid_sources[0x1e]	24311	1			T1	387		T5	41		T9	12
valid_sources[0x1f]	28899	1			T1	354		T5	41		T9	7
valid_sources[0x20]	27897	1			T1	344		T5	25		T9	5
valid_sources[0x21]	28405	1			T1	339		T5	27		T6	898
valid_sources[0x22]	25464	1			T1	361		T5	49		T9	4
valid_sources[0x23]	24459	1			T1	392		T5	30		T9	10
valid_sources[0x24]	26385	1			T1	383		T4	1		T5	41
valid_sources[0x25]	29619	1			T1	355		T5	39		T9	8
valid_sources[0x26]	25527	1			T1	366		T5	37		T9	6
valid_sources[0x27]	29864	1			T1	340		T5	34		T9	12
valid_sources[0x28]	26448	1			T1	351		T5	32		T9	7
valid_sources[0x29]	30968	1			T1	355		T5	19		T9	1
valid_sources[0x2a]	31248	1			T1	368		T5	29		T9	3
valid_sources[0x2b]	27851	1			T1	390		T5	34		T9	9
valid_sources[0x2c]	28686	1			T1	358		T5	40		T9	6
valid_sources[0x2d]	31007	1			T1	347		T5	22		T9	1
valid_sources[0x2e]	28229	1			T1	348		T3	35		T5	23
valid_sources[0x2f]	26980	1			T1	398		T5	41		T9	2
valid_sources[0x30]	27249	1			T1	351		T5	29		T9	4
valid_sources[0x31]	30903	1			T1	361		T5	48		T9	5
valid_sources[0x32]	28692	1			T1	374		T5	26		T9	3
valid_sources[0x33]	25301	1			T1	358		T5	35		T9	5
valid_sources[0x34]	26047	1			T1	351		T5	24		T9	2
valid_sources[0x35]	37519	1			T1	353		T5	25		T7	1
valid_sources[0x36]	24401	1			T1	388		T5	41		T9	5
valid_sources[0x37]	25694	1			T1	373		T5	31		T9	3
valid_sources[0x38]	24743	1			T1	338		T5	42		T9	13
valid_sources[0x39]	30091	1			T1	343		T5	38		T9	5
valid_sources[0x3a]	28123	1			T1	377		T5	34		T9	3
valid_sources[0x3b]	31631	1			T1	376		T4	1		T5	41
valid_sources[0x3c]	28301	1			T1	357		T5	35		T9	2
valid_sources[0x3d]	26970	1			T1	389		T5	34		T9	5
valid_sources[0x3e]	29030	1			T1	359		T5	38		T9	1
valid_sources[0x3f]	28042	1			T1	353		T5	42		T9	3
valid_sources[0x40]	25740	1			T1	359		T5	26		T9	7
valid_sources[0x41]	30279	1			T1	344		T5	26		T9	11
valid_sources[0x42]	25974	1			T1	372		T5	39		T9	8
valid_sources[0x43]	27532	1			T1	365		T5	39		T9	7
valid_sources[0x44]	26761	1			T1	376		T5	32		T9	10
valid_sources[0x45]	28312	1			T1	373		T5	37		T9	3
valid_sources[0x46]	26374	1			T1	339		T5	39		T9	5
valid_sources[0x47]	31823	1			T1	373		T3	452		T5	27
valid_sources[0x48]	29363	1			T1	387		T5	31		T9	3
valid_sources[0x49]	27545	1			T1	382		T4	1		T5	35
valid_sources[0x4a]	26531	1			T1	365		T5	31		T9	13
valid_sources[0x4b]	25346	1			T1	389		T5	29		T9	8
valid_sources[0x4c]	24588	1			T1	374		T5	25		T7	1
valid_sources[0x4d]	26074	1			T1	356		T5	39		T9	2
valid_sources[0x4e]	25739	1			T1	378		T5	25		T9	4
valid_sources[0x4f]	25199	1			T1	383		T5	45		T9	8
valid_sources[0x50]	28918	1			T1	365		T5	25		T7	1
valid_sources[0x51]	29500	1			T1	355		T5	32		T9	7
valid_sources[0x52]	26795	1			T1	349		T4	6		T5	41
valid_sources[0x53]	28171	1			T1	356		T5	26		T9	4
valid_sources[0x54]	29248	1			T1	363		T4	1		T5	27
valid_sources[0x55]	27145	1			T1	371		T5	32		T9	2
valid_sources[0x56]	26311	1			T1	375		T5	20		T9	3
valid_sources[0x57]	28583	1			T1	388		T5	23		T9	15
valid_sources[0x58]	27987	1			T1	365		T5	27		T9	4
valid_sources[0x59]	28104	1			T1	356		T5	38		T9	2
valid_sources[0x5a]	28585	1			T1	372		T5	25		T9	9
valid_sources[0x5b]	27140	1			T1	384		T5	54		T9	3
valid_sources[0x5c]	27083	1			T1	344		T5	35		T9	2
valid_sources[0x5d]	26160	1			T1	338		T5	28		T9	5
valid_sources[0x5e]	26816	1			T1	375		T5	31		T9	5
valid_sources[0x5f]	34795	1			T1	383		T5	32		T9	18
valid_sources[0x60]	28182	1			T1	352		T5	51		T9	1
valid_sources[0x61]	28095	1			T1	355		T5	30		T9	4
valid_sources[0x62]	27366	1			T1	339		T5	43		T9	4
valid_sources[0x63]	25908	1			T1	356		T5	37		T9	3
valid_sources[0x64]	25185	1			T1	386		T5	40		T9	4
valid_sources[0x65]	27071	1			T1	364		T5	42		T9	1
valid_sources[0x66]	29162	1			T1	381		T5	30		T9	4
valid_sources[0x67]	30221	1			T1	344		T5	31		T9	7
valid_sources[0x68]	27096	1			T1	347		T5	31		T9	5
valid_sources[0x69]	29996	1			T1	371		T2	452		T5	49
valid_sources[0x6a]	50111	1			T1	364		T2	643		T5	26
valid_sources[0x6b]	27669	1			T1	383		T5	32		T9	2
valid_sources[0x6c]	29191	1			T1	358		T5	31		T9	6
valid_sources[0x6d]	27533	1			T1	349		T5	34		T9	11
valid_sources[0x6e]	70393	1			T1	369		T5	38		T9	9
valid_sources[0x6f]	27143	1			T1	400		T5	41		T9	2
valid_sources[0x70]	26534	1			T1	310		T5	26		T9	3
valid_sources[0x71]	26197	1			T1	371		T5	33		T9	11
valid_sources[0x72]	27317	1			T1	383		T5	19		T9	5
valid_sources[0x73]	30265	1			T1	362		T3	1		T5	42
valid_sources[0x74]	27262	1			T1	358		T5	47		T9	7
valid_sources[0x75]	26330	1			T1	383		T5	34		T9	6
valid_sources[0x76]	25870	1			T1	356		T5	38		T9	10
valid_sources[0x77]	27175	1			T1	355		T5	36		T9	10
valid_sources[0x78]	29412	1			T1	360		T5	36		T9	8
valid_sources[0x79]	43499	1			T1	362		T5	46		T9	5
valid_sources[0x7a]	39630	1			T1	357		T5	29		T7	1
valid_sources[0x7b]	27492	1			T1	346		T5	40		T9	12
valid_sources[0x7c]	25942	1			T1	363		T5	34		T9	3
valid_sources[0x7d]	28580	1			T1	345		T5	31		T7	1
valid_sources[0x7e]	29334	1			T1	350		T5	31		T9	6
valid_sources[0x7f]	27335	1			T1	382		T5	31		T9	5
valid_sources[0x80]	26031	1			T1	367		T5	39		T9	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1061572

1

T1

46234

T2

102

T3

14

values[0x0]

all_enables

biggest_size

1504331

1

T1

457

T2

420

T3

453

values[0x1]

all_enables

biggest_size

1482940

1

T1

461

T2

458

T3

424