Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3260324

1

T1

46120

T2

116

T3

24

full_word

4050017

1

T1

47152

T2

980

T3

891

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7309991	1			T1	93272		T2	1096		T3	915
auto[TlIntgErrCmd]	115	1			T105	4		T106	4		T108	4
auto[TlIntgErrData]	115	1			T105	3		T106	1		T108	4
auto[TlIntgErrBoth]	120	1			T105	3		T106	5		T108	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4012961

1

T1

92343

T2

205

T3

35

auto[1]

3297380

1

T1

929

T2

891

T3

880

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	2950977	1			T1	46109		T2	103		T3	21
auto[TlIntgErrNone]	partial	auto[1]	309029	1			T1	11		T2	13		T3	3
auto[TlIntgErrNone]	full_word	auto[0]	1061818	1			T1	46234		T2	102		T3	14
auto[TlIntgErrNone]	full_word	auto[1]	2988167	1			T1	918		T2	878		T3	877
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T105	1		T106	2		T108	2
auto[TlIntgErrCmd]	partial	auto[1]	55	1			T105	3		T106	2		T108	2
auto[TlIntgErrCmd]	full_word	auto[0]	9	1			T164	2		T153	1		T166	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T164	1		T168	1		T153	1
auto[TlIntgErrData]	partial	auto[0]	50	1			T105	2		T106	1		T108	2
auto[TlIntgErrData]	partial	auto[1]	57	1			T105	1		T108	2		T164	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T169	1		T170	1		T171	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T153	1		T165	1		T172	1
auto[TlIntgErrBoth]	partial	auto[0]	53	1			T105	1		T106	4		T164	1
auto[TlIntgErrBoth]	partial	auto[1]	58	1			T105	1		T106	1		T108	2
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T165	1		T169	1		T170	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T105	1		T172	1		T170	1