Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
441914364 |
441907351 |
0 |
0 |
selKnown1 |
147179235 |
147178425 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441914364 |
441907351 |
0 |
0 |
T1 |
662466 |
662460 |
0 |
0 |
T2 |
45471 |
45465 |
0 |
0 |
T3 |
6819 |
6813 |
0 |
0 |
T4 |
3408 |
3404 |
0 |
0 |
T5 |
548550 |
548544 |
0 |
0 |
T6 |
365319 |
365313 |
0 |
0 |
T7 |
3 |
0 |
0 |
0 |
T8 |
3 |
0 |
0 |
0 |
T9 |
61095 |
61089 |
0 |
0 |
T10 |
650283 |
650277 |
0 |
0 |
T11 |
754569 |
2262456 |
0 |
0 |
T12 |
148649 |
444904 |
0 |
0 |
T13 |
40 |
58 |
0 |
0 |
T14 |
2 |
1 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
0 |
4 |
0 |
0 |
T17 |
0 |
2 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T19 |
0 |
3 |
0 |
0 |
T20 |
0 |
3 |
0 |
0 |
T21 |
0 |
1 |
0 |
0 |
T22 |
0 |
20 |
0 |
0 |
T23 |
0 |
2 |
0 |
0 |
T24 |
1 |
0 |
0 |
0 |
T25 |
1 |
0 |
0 |
0 |
T26 |
1 |
0 |
0 |
0 |
T27 |
1 |
0 |
0 |
0 |
T28 |
1 |
0 |
0 |
0 |
T29 |
1 |
0 |
0 |
0 |
T30 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
147179235 |
147178425 |
0 |
0 |
T1 |
220793 |
220792 |
0 |
0 |
T2 |
15148 |
15147 |
0 |
0 |
T3 |
2268 |
2267 |
0 |
0 |
T4 |
1135 |
1134 |
0 |
0 |
T5 |
182623 |
182622 |
0 |
0 |
T6 |
121746 |
121745 |
0 |
0 |
T9 |
20356 |
20355 |
0 |
0 |
T10 |
216572 |
216571 |
0 |
0 |
T11 |
753737 |
753736 |
0 |
0 |
T12 |
147955 |
147955 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_spi_in_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_spi_in_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 4 | 44.44 |
Logical | 9 | 4 | 44.44 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_clk_spi_in_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
147179235 |
147178425 |
0 |
0 |
selKnown1 |
0 |
0 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
147179235 |
147178425 |
0 |
0 |
T1 |
220793 |
220792 |
0 |
0 |
T2 |
15148 |
15147 |
0 |
0 |
T3 |
2268 |
2267 |
0 |
0 |
T4 |
1135 |
1134 |
0 |
0 |
T5 |
182623 |
182622 |
0 |
0 |
T6 |
121746 |
121745 |
0 |
0 |
T9 |
20356 |
20355 |
0 |
0 |
T10 |
216572 |
216571 |
0 |
0 |
T11 |
753737 |
753736 |
0 |
0 |
T12 |
147955 |
147955 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_spi_out_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_spi_out_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 4 | 44.44 |
Logical | 9 | 4 | 44.44 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_clk_spi_out_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
147180173 |
147179217 |
0 |
0 |
selKnown1 |
0 |
0 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
147180173 |
147179217 |
0 |
0 |
T1 |
220794 |
220793 |
0 |
0 |
T2 |
15149 |
15148 |
0 |
0 |
T3 |
2269 |
2268 |
0 |
0 |
T4 |
1136 |
1135 |
0 |
0 |
T5 |
182624 |
182623 |
0 |
0 |
T6 |
121747 |
121746 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
20357 |
20356 |
0 |
0 |
T10 |
216573 |
216572 |
0 |
0 |
T11 |
0 |
753737 |
0 |
0 |
T12 |
0 |
147955 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_csb_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_csb_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 4 | 44.44 |
Logical | 9 | 4 | 44.44 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_clk_csb_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
62319 |
61363 |
0 |
0 |
selKnown1 |
0 |
0 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
62319 |
61363 |
0 |
0 |
T1 |
29 |
28 |
0 |
0 |
T2 |
9 |
8 |
0 |
0 |
T3 |
5 |
4 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
227 |
226 |
0 |
0 |
T6 |
27 |
26 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
9 |
8 |
0 |
0 |
T10 |
189 |
188 |
0 |
0 |
T11 |
0 |
416 |
0 |
0 |
T12 |
0 |
347 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_csb_rst_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_csb_rst_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 4 | 44.44 |
Logical | 9 | 4 | 44.44 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_csb_rst_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
61363 |
60689 |
0 |
0 |
selKnown1 |
0 |
0 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
61363 |
60689 |
0 |
0 |
T1 |
28 |
27 |
0 |
0 |
T2 |
8 |
7 |
0 |
0 |
T3 |
4 |
3 |
0 |
0 |
T5 |
226 |
225 |
0 |
0 |
T6 |
26 |
25 |
0 |
0 |
T9 |
8 |
7 |
0 |
0 |
T10 |
188 |
187 |
0 |
0 |
T11 |
416 |
415 |
0 |
0 |
T12 |
347 |
346 |
0 |
0 |
T13 |
20 |
19 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_csb_rst_out_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_csb_rst_out_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 4 | 44.44 |
Logical | 9 | 4 | 44.44 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_csb_rst_out_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
60473 |
59858 |
0 |
0 |
selKnown1 |
0 |
0 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
60473 |
59858 |
0 |
0 |
T1 |
28 |
27 |
0 |
0 |
T2 |
8 |
7 |
0 |
0 |
T3 |
4 |
3 |
0 |
0 |
T5 |
226 |
225 |
0 |
0 |
T6 |
26 |
25 |
0 |
0 |
T9 |
8 |
7 |
0 |
0 |
T10 |
188 |
187 |
0 |
0 |
T11 |
416 |
415 |
0 |
0 |
T12 |
347 |
346 |
0 |
0 |
T13 |
20 |
19 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tpm_csb_rst_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_tpm_csb_rst_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 4 | 44.44 |
Logical | 9 | 4 | 44.44 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T4,T12,T31 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T4,T12,T31 |
Assert Coverage for Instance : tb.dut.u_tpm_csb_rst_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
63466 |
63083 |
0 |
0 |
selKnown1 |
0 |
0 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
63466 |
63083 |
0 |
0 |
T4 |
13 |
12 |
0 |
0 |
T12 |
479 |
478 |
0 |
0 |
T14 |
76 |
75 |
0 |
0 |
T27 |
7 |
6 |
0 |
0 |
T30 |
49 |
48 |
0 |
0 |
T31 |
488 |
487 |
0 |
0 |
T32 |
121 |
120 |
0 |
0 |
T33 |
7 |
6 |
0 |
0 |
T34 |
11 |
10 |
0 |
0 |
T35 |
373 |
372 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tpm_rst_out_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_tpm_rst_out_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 4 | 44.44 |
Logical | 9 | 4 | 44.44 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T4,T12,T31 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T4,T12,T31 |
Assert Coverage for Instance : tb.dut.u_tpm_rst_out_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
62549 |
62225 |
0 |
0 |
selKnown1 |
0 |
0 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
62549 |
62225 |
0 |
0 |
T4 |
13 |
12 |
0 |
0 |
T12 |
479 |
478 |
0 |
0 |
T14 |
69 |
68 |
0 |
0 |
T30 |
49 |
48 |
0 |
0 |
T31 |
488 |
487 |
0 |
0 |
T32 |
121 |
120 |
0 |
0 |
T33 |
7 |
6 |
0 |
0 |
T34 |
11 |
10 |
0 |
0 |
T35 |
373 |
372 |
0 |
0 |
T36 |
267 |
266 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tpm_csb_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_tpm_csb_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 4 | 44.44 |
Logical | 9 | 4 | 44.44 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T4,T12,T31 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T4,T12,T31 |
Assert Coverage for Instance : tb.dut.u_tpm_csb_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
63465 |
63082 |
0 |
0 |
selKnown1 |
0 |
0 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
63465 |
63082 |
0 |
0 |
T4 |
13 |
12 |
0 |
0 |
T12 |
479 |
478 |
0 |
0 |
T14 |
76 |
75 |
0 |
0 |
T27 |
7 |
6 |
0 |
0 |
T30 |
49 |
48 |
0 |
0 |
T31 |
488 |
487 |
0 |
0 |
T32 |
121 |
120 |
0 |
0 |
T33 |
7 |
6 |
0 |
0 |
T34 |
11 |
10 |
0 |
0 |
T35 |
373 |
372 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_spid_status.u_csb_rst_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_spid_status.u_csb_rst_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 4 | 44.44 |
Logical | 9 | 4 | 44.44 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_spid_status.u_csb_rst_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
1148 |
192 |
0 |
0 |
selKnown1 |
0 |
0 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1148 |
192 |
0 |
0 |
T14 |
2 |
1 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
0 |
4 |
0 |
0 |
T17 |
0 |
2 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T19 |
0 |
3 |
0 |
0 |
T20 |
0 |
3 |
0 |
0 |
T21 |
0 |
1 |
0 |
0 |
T22 |
0 |
20 |
0 |
0 |
T23 |
0 |
2 |
0 |
0 |
T24 |
1 |
0 |
0 |
0 |
T25 |
1 |
0 |
0 |
0 |
T26 |
1 |
0 |
0 |
0 |
T27 |
1 |
0 |
0 |
0 |
T28 |
1 |
0 |
0 |
0 |
T29 |
1 |
0 |
0 |
0 |
T30 |
1 |
0 |
0 |
0 |
T37 |
1 |
0 |
0 |
0 |
T38 |
1 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_spi.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_spi.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_clk_spi.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
147180173 |
147179217 |
0 |
0 |
selKnown1 |
147179235 |
147178425 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
147180173 |
147179217 |
0 |
0 |
T1 |
220794 |
220793 |
0 |
0 |
T2 |
15149 |
15148 |
0 |
0 |
T3 |
2269 |
2268 |
0 |
0 |
T4 |
1136 |
1135 |
0 |
0 |
T5 |
182624 |
182623 |
0 |
0 |
T6 |
121747 |
121746 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
20357 |
20356 |
0 |
0 |
T10 |
216573 |
216572 |
0 |
0 |
T11 |
0 |
753737 |
0 |
0 |
T12 |
0 |
147955 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
147179235 |
147178425 |
0 |
0 |
T1 |
220793 |
220792 |
0 |
0 |
T2 |
15148 |
15147 |
0 |
0 |
T3 |
2268 |
2267 |
0 |
0 |
T4 |
1135 |
1134 |
0 |
0 |
T5 |
182623 |
182622 |
0 |
0 |
T6 |
121746 |
121745 |
0 |
0 |
T9 |
20356 |
20355 |
0 |
0 |
T10 |
216572 |
216571 |
0 |
0 |
T11 |
753737 |
753736 |
0 |
0 |
T12 |
147955 |
147955 |
0 |
0 |