Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	419319913	2797041	0	0
DepthKnown_A	419319913	419191984	0	0
RvalidKnown_A	419319913	419191984	0	0
WreadyKnown_A	419319913	419191984	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419319913	2797041	0	0
T1	154741	832	0	0
T2	7128	1663	0	0
T3	4435	1669	0	0
T4	9814	0	0	0
T5	148651	9979	0	0
T6	33187	832	0	0
T7	1050	0	0	0
T8	1189	0	0	0
T9	23171	832	0	0
T10	901261	7500	0	0
T11	0	12476	0	0
T12	0	19986	0	0
T13	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419319913	419191984	0	0
T1	154741	154733	0	0
T2	7128	7028	0	0
T3	4435	4347	0	0
T4	9814	9760	0	0
T5	148651	148642	0	0
T6	33187	33108	0	0
T7	1050	986	0	0
T8	1189	1093	0	0
T9	23171	23091	0	0
T10	901261	901189	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419319913	419191984	0	0
T1	154741	154733	0	0
T2	7128	7028	0	0
T3	4435	4347	0	0
T4	9814	9760	0	0
T5	148651	148642	0	0
T6	33187	33108	0	0
T7	1050	986	0	0
T8	1189	1093	0	0
T9	23171	23091	0	0
T10	901261	901189	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419319913	419191984	0	0
T1	154741	154733	0	0
T2	7128	7028	0	0
T3	4435	4347	0	0
T4	9814	9760	0	0
T5	148651	148642	0	0
T6	33187	33108	0	0
T7	1050	986	0	0
T8	1189	1093	0	0
T9	23171	23091	0	0
T10	901261	901189	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	419319913	3112456	0	0
DepthKnown_A	419319913	419191984	0	0
RvalidKnown_A	419319913	419191984	0	0
WreadyKnown_A	419319913	419191984	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419319913	3112456	0	0
T1	154741	832	0	0
T2	7128	832	0	0
T3	4435	838	0	0
T4	9814	0	0	0
T5	148651	5824	0	0
T6	33187	832	0	0
T7	1050	0	0	0
T8	1189	0	0	0
T9	23171	832	0	0
T10	901261	5007	0	0
T11	0	9152	0	0
T12	0	24090	0	0
T13	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419319913	419191984	0	0
T1	154741	154733	0	0
T2	7128	7028	0	0
T3	4435	4347	0	0
T4	9814	9760	0	0
T5	148651	148642	0	0
T6	33187	33108	0	0
T7	1050	986	0	0
T8	1189	1093	0	0
T9	23171	23091	0	0
T10	901261	901189	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419319913	419191984	0	0
T1	154741	154733	0	0
T2	7128	7028	0	0
T3	4435	4347	0	0
T4	9814	9760	0	0
T5	148651	148642	0	0
T6	33187	33108	0	0
T7	1050	986	0	0
T8	1189	1093	0	0
T9	23171	23091	0	0
T10	901261	901189	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419319913	419191984	0	0
T1	154741	154733	0	0
T2	7128	7028	0	0
T3	4435	4347	0	0
T4	9814	9760	0	0
T5	148651	148642	0	0
T6	33187	33108	0	0
T7	1050	986	0	0
T8	1189	1093	0	0
T9	23171	23091	0	0
T10	901261	901189	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	419319913	174759	0	0
DepthKnown_A	419319913	419191984	0	0
RvalidKnown_A	419319913	419191984	0	0
WreadyKnown_A	419319913	419191984	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419319913	174759	0	0
T5	148651	228	0	0
T6	33187	0	0	0
T7	1050	0	0	0
T8	1189	0	0	0
T9	23171	0	0	0
T10	901261	256	0	0
T11	448793	416	0	0
T12	796412	1169	0	0
T13	524889	0	0	0
T31	0	1363	0	0
T32	0	326	0	0
T34	0	26	0	0
T35	0	775	0	0
T41	469575	353	0	0
T42	0	96	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419319913	419191984	0	0
T1	154741	154733	0	0
T2	7128	7028	0	0
T3	4435	4347	0	0
T4	9814	9760	0	0
T5	148651	148642	0	0
T6	33187	33108	0	0
T7	1050	986	0	0
T8	1189	1093	0	0
T9	23171	23091	0	0
T10	901261	901189	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419319913	419191984	0	0
T1	154741	154733	0	0
T2	7128	7028	0	0
T3	4435	4347	0	0
T4	9814	9760	0	0
T5	148651	148642	0	0
T6	33187	33108	0	0
T7	1050	986	0	0
T8	1189	1093	0	0
T9	23171	23091	0	0
T10	901261	901189	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419319913	419191984	0	0
T1	154741	154733	0	0
T2	7128	7028	0	0
T3	4435	4347	0	0
T4	9814	9760	0	0
T5	148651	148642	0	0
T6	33187	33108	0	0
T7	1050	986	0	0
T8	1189	1093	0	0
T9	23171	23091	0	0
T10	901261	901189	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	419319913	435144	0	0
DepthKnown_A	419319913	419191984	0	0
RvalidKnown_A	419319913	419191984	0	0
WreadyKnown_A	419319913	419191984	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419319913	435144	0	0
T5	148651	228	0	0
T6	33187	0	0	0
T7	1050	0	0	0
T8	1189	0	0	0
T9	23171	0	0	0
T10	901261	701	0	0
T11	448793	416	0	0
T12	796412	5374	0	0
T13	524889	0	0	0
T31	0	6273	0	0
T32	0	325	0	0
T34	0	26	0	0
T35	0	775	0	0
T41	469575	1588	0	0
T42	0	96	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419319913	419191984	0	0
T1	154741	154733	0	0
T2	7128	7028	0	0
T3	4435	4347	0	0
T4	9814	9760	0	0
T5	148651	148642	0	0
T6	33187	33108	0	0
T7	1050	986	0	0
T8	1189	1093	0	0
T9	23171	23091	0	0
T10	901261	901189	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419319913	419191984	0	0
T1	154741	154733	0	0
T2	7128	7028	0	0
T3	4435	4347	0	0
T4	9814	9760	0	0
T5	148651	148642	0	0
T6	33187	33108	0	0
T7	1050	986	0	0
T8	1189	1093	0	0
T9	23171	23091	0	0
T10	901261	901189	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419319913	419191984	0	0
T1	154741	154733	0	0
T2	7128	7028	0	0
T3	4435	4347	0	0
T4	9814	9760	0	0
T5	148651	148642	0	0
T6	33187	33108	0	0
T7	1050	986	0	0
T8	1189	1093	0	0
T9	23171	23091	0	0
T10	901261	901189	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	419319913	5667222	0	0
DepthKnown_A	419319913	419191984	0	0
RvalidKnown_A	419319913	419191984	0	0
WreadyKnown_A	419319913	419191984	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419319913	5667222	0	0
T1	154741	92440	0	0
T2	7128	264	0	0
T3	4435	92	0	0
T4	9814	41	0	0
T5	148651	2684	0	0
T6	33187	66	0	0
T7	1050	15	0	0
T8	1189	16	0	0
T9	23171	693	0	0
T10	901261	1762	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419319913	419191984	0	0
T1	154741	154733	0	0
T2	7128	7028	0	0
T3	4435	4347	0	0
T4	9814	9760	0	0
T5	148651	148642	0	0
T6	33187	33108	0	0
T7	1050	986	0	0
T8	1189	1093	0	0
T9	23171	23091	0	0
T10	901261	901189	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419319913	419191984	0	0
T1	154741	154733	0	0
T2	7128	7028	0	0
T3	4435	4347	0	0
T4	9814	9760	0	0
T5	148651	148642	0	0
T6	33187	33108	0	0
T7	1050	986	0	0
T8	1189	1093	0	0
T9	23171	23091	0	0
T10	901261	901189	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419319913	419191984	0	0
T1	154741	154733	0	0
T2	7128	7028	0	0
T3	4435	4347	0	0
T4	9814	9760	0	0
T5	148651	148642	0	0
T6	33187	33108	0	0
T7	1050	986	0	0
T8	1189	1093	0	0
T9	23171	23091	0	0
T10	901261	901189	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	419319913	11855781	0	0
DepthKnown_A	419319913	419191984	0	0
RvalidKnown_A	419319913	419191984	0	0
WreadyKnown_A	419319913	419191984	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419319913	11855781	0	0
T1	154741	92440	0	0
T2	7128	792	0	0
T3	4435	375	0	0
T4	9814	41	0	0
T5	148651	2682	0	0
T6	33187	66	0	0
T7	1050	52	0	0
T8	1189	62	0	0
T9	23171	693	0	0
T10	901261	4860	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419319913	419191984	0	0
T1	154741	154733	0	0
T2	7128	7028	0	0
T3	4435	4347	0	0
T4	9814	9760	0	0
T5	148651	148642	0	0
T6	33187	33108	0	0
T7	1050	986	0	0
T8	1189	1093	0	0
T9	23171	23091	0	0
T10	901261	901189	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419319913	419191984	0	0
T1	154741	154733	0	0
T2	7128	7028	0	0
T3	4435	4347	0	0
T4	9814	9760	0	0
T5	148651	148642	0	0
T6	33187	33108	0	0
T7	1050	986	0	0
T8	1189	1093	0	0
T9	23171	23091	0	0
T10	901261	901189	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419319913	419191984	0	0
T1	154741	154733	0	0
T2	7128	7028	0	0
T3	4435	4347	0	0
T4	9814	9760	0	0
T5	148651	148642	0	0
T6	33187	33108	0	0
T7	1050	986	0	0
T8	1189	1093	0	0
T9	23171	23091	0	0
T10	901261	901189	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0