Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T31,T32
1	0	Covered	T12,T31,T32

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T12,T31
1	0	Unreachable
1	1	Covered	T12,T31,T32

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T10,T11

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T10,T11
1	0	Covered	T5,T10,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T5,T10,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T10,T11

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T10,T11
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	711589885	563013849	0	0
CheckNGreaterZero_A	2868	2868	0	0
GntImpliesReady_A	711589885	3577563	0	0
GntImpliesValid_A	711589885	3577563	0	0
GrantKnown_A	711589885	563013849	0	0
IdxKnown_A	711589885	563013849	0	0
IndexIsCorrect_A	711589885	3577563	0	0
LockArbDecision_A	711589885	0	0	0
NoReadyValidNoGrant_A	711589885	0	0	0
ReadyAndValidImplyGrant_A	711589885	3577563	0	0
ReqAndReadyImplyGrant_A	711589885	3577563	0	0
ReqImpliesValid_A	711589885	3577563	0	0
ReqStaysHighUntilGranted0_M	711589885	0	0	0
RoundRobin_A	711589885	4	0	956
ValidKnown_A	711589885	563013849	0	0
gen_data_port_assertion.DataFlow_A	711589885	3577563	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711589885	563013849	0	0
T1	375534	375201	0	0
T2	22276	22176	0	0
T3	6703	6615	0	0
T4	12084	10696	0	0
T5	513897	330253	0	0
T6	276679	154854	0	0
T7	1050	986	0	0
T8	1189	1093	0	0
T9	63883	43447	0	0
T10	1334405	1115700	0	0
T11	1507474	751481	0	0
T12	295910	460090	0	0
T13	128925	128714	0	0
T14	0	69176	0	0
T30	0	14264	0	0
T31	0	258712	0	0
T32	0	33208	0	0
T33	0	504	0	0
T34	0	1568	0	0
T35	0	108424	0	0
T36	0	207168	0	0
T41	826598	0	0	0
T45	92406	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2868	2868	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711589885	3577563	0	0
T1	154741	832	0	0
T2	7128	832	0	0
T3	4435	832	0	0
T4	9814	0	0	0
T5	331274	7022	0	0
T6	154933	832	0	0
T7	1050	0	0	0
T8	1189	0	0	0
T9	43527	832	0	0
T10	1117833	9377	0	0
T11	753737	17684	0	0
T12	295910	25067	0	0
T13	257850	832	0	0
T14	0	8378	0	0
T30	0	531	0	0
T31	1203774	9371	0	0
T32	174024	1871	0	0
T33	836	0	0	0
T34	0	106	0	0
T35	0	4805	0	0
T36	0	3655	0	0
T41	1653196	5536	0	0
T42	0	393	0	0
T45	184812	0	0	0
T46	122664	0	0	0
T47	29760	0	0	0
T48	17536	0	0	0
T49	0	2709	0	0
T50	0	6069	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711589885	3577563	0	0
T1	154741	832	0	0
T2	7128	832	0	0
T3	4435	832	0	0
T4	9814	0	0	0
T5	331274	7022	0	0
T6	154933	832	0	0
T7	1050	0	0	0
T8	1189	0	0	0
T9	43527	832	0	0
T10	1117833	9377	0	0
T11	753737	17684	0	0
T12	295910	25067	0	0
T13	257850	832	0	0
T14	0	8378	0	0
T30	0	531	0	0
T31	1203774	9371	0	0
T32	174024	1871	0	0
T33	836	0	0	0
T34	0	106	0	0
T35	0	4805	0	0
T36	0	3655	0	0
T41	1653196	5536	0	0
T42	0	393	0	0
T45	184812	0	0	0
T46	122664	0	0	0
T47	29760	0	0	0
T48	17536	0	0	0
T49	0	2709	0	0
T50	0	6069	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711589885	563013849	0	0
T1	375534	375201	0	0
T2	22276	22176	0	0
T3	6703	6615	0	0
T4	12084	10696	0	0
T5	513897	330253	0	0
T6	276679	154854	0	0
T7	1050	986	0	0
T8	1189	1093	0	0
T9	63883	43447	0	0
T10	1334405	1115700	0	0
T11	1507474	751481	0	0
T12	295910	460090	0	0
T13	128925	128714	0	0
T14	0	69176	0	0
T30	0	14264	0	0
T31	0	258712	0	0
T32	0	33208	0	0
T33	0	504	0	0
T34	0	1568	0	0
T35	0	108424	0	0
T36	0	207168	0	0
T41	826598	0	0	0
T45	92406	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711589885	563013849	0	0
T1	375534	375201	0	0
T2	22276	22176	0	0
T3	6703	6615	0	0
T4	12084	10696	0	0
T5	513897	330253	0	0
T6	276679	154854	0	0
T7	1050	986	0	0
T8	1189	1093	0	0
T9	63883	43447	0	0
T10	1334405	1115700	0	0
T11	1507474	751481	0	0
T12	295910	460090	0	0
T13	128925	128714	0	0
T14	0	69176	0	0
T30	0	14264	0	0
T31	0	258712	0	0
T32	0	33208	0	0
T33	0	504	0	0
T34	0	1568	0	0
T35	0	108424	0	0
T36	0	207168	0	0
T41	826598	0	0	0
T45	92406	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711589885	3577563	0	0
T1	154741	832	0	0
T2	7128	832	0	0
T3	4435	832	0	0
T4	9814	0	0	0
T5	331274	7022	0	0
T6	154933	832	0	0
T7	1050	0	0	0
T8	1189	0	0	0
T9	43527	832	0	0
T10	1117833	9377	0	0
T11	753737	17684	0	0
T12	295910	25067	0	0
T13	257850	832	0	0
T14	0	8378	0	0
T30	0	531	0	0
T31	1203774	9371	0	0
T32	174024	1871	0	0
T33	836	0	0	0
T34	0	106	0	0
T35	0	4805	0	0
T36	0	3655	0	0
T41	1653196	5536	0	0
T42	0	393	0	0
T45	184812	0	0	0
T46	122664	0	0	0
T47	29760	0	0	0
T48	17536	0	0	0
T49	0	2709	0	0
T50	0	6069	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711589885	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711589885	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711589885	3577563	0	0
T1	154741	832	0	0
T2	7128	832	0	0
T3	4435	832	0	0
T4	9814	0	0	0
T5	331274	7022	0	0
T6	154933	832	0	0
T7	1050	0	0	0
T8	1189	0	0	0
T9	43527	832	0	0
T10	1117833	9377	0	0
T11	753737	17684	0	0
T12	295910	25067	0	0
T13	257850	832	0	0
T14	0	8378	0	0
T30	0	531	0	0
T31	1203774	9371	0	0
T32	174024	1871	0	0
T33	836	0	0	0
T34	0	106	0	0
T35	0	4805	0	0
T36	0	3655	0	0
T41	1653196	5536	0	0
T42	0	393	0	0
T45	184812	0	0	0
T46	122664	0	0	0
T47	29760	0	0	0
T48	17536	0	0	0
T49	0	2709	0	0
T50	0	6069	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711589885	3577563	0	0
T1	154741	832	0	0
T2	7128	832	0	0
T3	4435	832	0	0
T4	9814	0	0	0
T5	331274	7022	0	0
T6	154933	832	0	0
T7	1050	0	0	0
T8	1189	0	0	0
T9	43527	832	0	0
T10	1117833	9377	0	0
T11	753737	17684	0	0
T12	295910	25067	0	0
T13	257850	832	0	0
T14	0	8378	0	0
T30	0	531	0	0
T31	1203774	9371	0	0
T32	174024	1871	0	0
T33	836	0	0	0
T34	0	106	0	0
T35	0	4805	0	0
T36	0	3655	0	0
T41	1653196	5536	0	0
T42	0	393	0	0
T45	184812	0	0	0
T46	122664	0	0	0
T47	29760	0	0	0
T48	17536	0	0	0
T49	0	2709	0	0
T50	0	6069	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711589885	3577563	0	0
T1	154741	832	0	0
T2	7128	832	0	0
T3	4435	832	0	0
T4	9814	0	0	0
T5	331274	7022	0	0
T6	154933	832	0	0
T7	1050	0	0	0
T8	1189	0	0	0
T9	43527	832	0	0
T10	1117833	9377	0	0
T11	753737	17684	0	0
T12	295910	25067	0	0
T13	257850	832	0	0
T14	0	8378	0	0
T30	0	531	0	0
T31	1203774	9371	0	0
T32	174024	1871	0	0
T33	836	0	0	0
T34	0	106	0	0
T35	0	4805	0	0
T36	0	3655	0	0
T41	1653196	5536	0	0
T42	0	393	0	0
T45	184812	0	0	0
T46	122664	0	0	0
T47	29760	0	0	0
T48	17536	0	0	0
T49	0	2709	0	0
T50	0	6069	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	711589885	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711589885	4	0	956
T51	699869	1	0	1
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	206526	0	0	1
T56	96887	0	0	1
T57	124440	0	0	1
T58	12976	0	0	1
T59	905435	0	0	1
T60	33246	0	0	1
T61	2520	0	0	1
T62	808	0	0	1
T63	1117	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711589885	563013849	0	0
T1	375534	375201	0	0
T2	22276	22176	0	0
T3	6703	6615	0	0
T4	12084	10696	0	0
T5	513897	330253	0	0
T6	276679	154854	0	0
T7	1050	986	0	0
T8	1189	1093	0	0
T9	63883	43447	0	0
T10	1334405	1115700	0	0
T11	1507474	751481	0	0
T12	295910	460090	0	0
T13	128925	128714	0	0
T14	0	69176	0	0
T30	0	14264	0	0
T31	0	258712	0	0
T32	0	33208	0	0
T33	0	504	0	0
T34	0	1568	0	0
T35	0	108424	0	0
T36	0	207168	0	0
T41	826598	0	0	0
T45	92406	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711589885	3577563	0	0
T1	154741	832	0	0
T2	7128	832	0	0
T3	4435	832	0	0
T4	9814	0	0	0
T5	331274	7022	0	0
T6	154933	832	0	0
T7	1050	0	0	0
T8	1189	0	0	0
T9	43527	832	0	0
T10	1117833	9377	0	0
T11	753737	17684	0	0
T12	295910	25067	0	0
T13	257850	832	0	0
T14	0	8378	0	0
T30	0	531	0	0
T31	1203774	9371	0	0
T32	174024	1871	0	0
T33	836	0	0	0
T34	0	106	0	0
T35	0	4805	0	0
T36	0	3655	0	0
T41	1653196	5536	0	0
T42	0	393	0	0
T45	184812	0	0	0
T46	122664	0	0	0
T47	29760	0	0	0
T48	17536	0	0	0
T49	0	2709	0	0
T50	0	6069	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T31,T32
1	0	Covered	T12,T31,T32

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T12,T31
1	0	Unreachable
1	1	Covered	T12,T31,T32

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T12,T31,T32
0	0	1	Unreachable
0	0	0	Covered	T4,T12,T31

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T12,T31,T32
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T12,T31,T32
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	147179235	29152954	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	147179235	589922	0	0
GntImpliesValid_A	147179235	589922	0	0
GrantKnown_A	147179235	29152954	0	0
IdxKnown_A	147179235	29152954	0	0
IndexIsCorrect_A	147179235	589922	0	0
LockArbDecision_A	147179235	0	0	0
NoReadyValidNoGrant_A	147179235	0	0	0
ReadyAndValidImplyGrant_A	147179235	589922	0	0
ReqAndReadyImplyGrant_A	147179235	589922	0	0
ReqImpliesValid_A	147179235	589922	0	0
ReqStaysHighUntilGranted0_M	147179235	0	0	0
RoundRobin_A	147179235	0	0	0
ValidKnown_A	147179235	29152954	0	0
gen_data_port_assertion.DataFlow_A	147179235	589922	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147179235	29152954	0	0
T4	1135	936	0	0
T5	182623	0	0	0
T6	121746	0	0	0
T9	20356	0	0	0
T10	216572	0	0	0
T11	753737	0	0	0
T12	147955	348032	0	0
T13	128925	0	0	0
T14	0	69176	0	0
T30	0	14264	0	0
T31	0	258712	0	0
T32	0	33208	0	0
T33	0	504	0	0
T34	0	1568	0	0
T35	0	108424	0	0
T36	0	207168	0	0
T41	826598	0	0	0
T45	92406	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147179235	589922	0	0
T12	147955	5357	0	0
T13	128925	0	0	0
T14	0	703	0	0
T30	0	531	0	0
T31	601887	6513	0	0
T32	174024	1369	0	0
T33	836	0	0	0
T34	0	106	0	0
T35	0	4805	0	0
T36	0	3655	0	0
T41	826598	0	0	0
T45	92406	0	0	0
T46	122664	0	0	0
T47	29760	0	0	0
T48	17536	0	0	0
T49	0	2709	0	0
T50	0	6069	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147179235	589922	0	0
T12	147955	5357	0	0
T13	128925	0	0	0
T14	0	703	0	0
T30	0	531	0	0
T31	601887	6513	0	0
T32	174024	1369	0	0
T33	836	0	0	0
T34	0	106	0	0
T35	0	4805	0	0
T36	0	3655	0	0
T41	826598	0	0	0
T45	92406	0	0	0
T46	122664	0	0	0
T47	29760	0	0	0
T48	17536	0	0	0
T49	0	2709	0	0
T50	0	6069	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147179235	29152954	0	0
T4	1135	936	0	0
T5	182623	0	0	0
T6	121746	0	0	0
T9	20356	0	0	0
T10	216572	0	0	0
T11	753737	0	0	0
T12	147955	348032	0	0
T13	128925	0	0	0
T14	0	69176	0	0
T30	0	14264	0	0
T31	0	258712	0	0
T32	0	33208	0	0
T33	0	504	0	0
T34	0	1568	0	0
T35	0	108424	0	0
T36	0	207168	0	0
T41	826598	0	0	0
T45	92406	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147179235	29152954	0	0
T4	1135	936	0	0
T5	182623	0	0	0
T6	121746	0	0	0
T9	20356	0	0	0
T10	216572	0	0	0
T11	753737	0	0	0
T12	147955	348032	0	0
T13	128925	0	0	0
T14	0	69176	0	0
T30	0	14264	0	0
T31	0	258712	0	0
T32	0	33208	0	0
T33	0	504	0	0
T34	0	1568	0	0
T35	0	108424	0	0
T36	0	207168	0	0
T41	826598	0	0	0
T45	92406	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147179235	589922	0	0
T12	147955	5357	0	0
T13	128925	0	0	0
T14	0	703	0	0
T30	0	531	0	0
T31	601887	6513	0	0
T32	174024	1369	0	0
T33	836	0	0	0
T34	0	106	0	0
T35	0	4805	0	0
T36	0	3655	0	0
T41	826598	0	0	0
T45	92406	0	0	0
T46	122664	0	0	0
T47	29760	0	0	0
T48	17536	0	0	0
T49	0	2709	0	0
T50	0	6069	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147179235	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147179235	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147179235	589922	0	0
T12	147955	5357	0	0
T13	128925	0	0	0
T14	0	703	0	0
T30	0	531	0	0
T31	601887	6513	0	0
T32	174024	1369	0	0
T33	836	0	0	0
T34	0	106	0	0
T35	0	4805	0	0
T36	0	3655	0	0
T41	826598	0	0	0
T45	92406	0	0	0
T46	122664	0	0	0
T47	29760	0	0	0
T48	17536	0	0	0
T49	0	2709	0	0
T50	0	6069	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147179235	589922	0	0
T12	147955	5357	0	0
T13	128925	0	0	0
T14	0	703	0	0
T30	0	531	0	0
T31	601887	6513	0	0
T32	174024	1369	0	0
T33	836	0	0	0
T34	0	106	0	0
T35	0	4805	0	0
T36	0	3655	0	0
T41	826598	0	0	0
T45	92406	0	0	0
T46	122664	0	0	0
T47	29760	0	0	0
T48	17536	0	0	0
T49	0	2709	0	0
T50	0	6069	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147179235	589922	0	0
T12	147955	5357	0	0
T13	128925	0	0	0
T14	0	703	0	0
T30	0	531	0	0
T31	601887	6513	0	0
T32	174024	1369	0	0
T33	836	0	0	0
T34	0	106	0	0
T35	0	4805	0	0
T36	0	3655	0	0
T41	826598	0	0	0
T45	92406	0	0	0
T46	122664	0	0	0
T47	29760	0	0	0
T48	17536	0	0	0
T49	0	2709	0	0
T50	0	6069	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	147179235	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147179235	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147179235	29152954	0	0
T4	1135	936	0	0
T5	182623	0	0	0
T6	121746	0	0	0
T9	20356	0	0	0
T10	216572	0	0	0
T11	753737	0	0	0
T12	147955	348032	0	0
T13	128925	0	0	0
T14	0	69176	0	0
T30	0	14264	0	0
T31	0	258712	0	0
T32	0	33208	0	0
T33	0	504	0	0
T34	0	1568	0	0
T35	0	108424	0	0
T36	0	207168	0	0
T41	826598	0	0	0
T45	92406	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147179235	589922	0	0
T12	147955	5357	0	0
T13	128925	0	0	0
T14	0	703	0	0
T30	0	531	0	0
T31	601887	6513	0	0
T32	174024	1369	0	0
T33	836	0	0	0
T34	0	106	0	0
T35	0	4805	0	0
T36	0	3655	0	0
T41	826598	0	0	0
T45	92406	0	0	0
T46	122664	0	0	0
T47	29760	0	0	0
T48	17536	0	0	0
T49	0	2709	0	0
T50	0	6069	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T10,T11

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T10,T11
1	0	Covered	T5,T10,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T5,T10,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T10,T11
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T10,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	147179235	116716496	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	147179235	798930	0	0
GntImpliesValid_A	147179235	798930	0	0
GrantKnown_A	147179235	116716496	0	0
IdxKnown_A	147179235	116716496	0	0
IndexIsCorrect_A	147179235	798930	0	0
LockArbDecision_A	147179235	0	0	0
NoReadyValidNoGrant_A	147179235	0	0	0
ReadyAndValidImplyGrant_A	147179235	798930	0	0
ReqAndReadyImplyGrant_A	147179235	798930	0	0
ReqImpliesValid_A	147179235	798930	0	0
ReqStaysHighUntilGranted0_M	147179235	0	0	0
RoundRobin_A	147179235	0	0	0
ValidKnown_A	147179235	116716496	0	0
gen_data_port_assertion.DataFlow_A	147179235	798930	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147179235	116716496	0	0
T1	220793	220468	0	0
T2	15148	15148	0	0
T3	2268	2268	0	0
T4	1135	0	0	0
T5	182623	181611	0	0
T6	121746	121746	0	0
T9	20356	20356	0	0
T10	216572	214511	0	0
T11	753737	751481	0	0
T12	147955	112058	0	0
T13	0	128714	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147179235	798930	0	0
T5	182623	942	0	0
T6	121746	0	0	0
T9	20356	0	0	0
T10	216572	4114	0	0
T11	753737	8094	0	0
T12	147955	5061	0	0
T13	128925	0	0	0
T14	0	7675	0	0
T24	0	1302	0	0
T31	601887	2858	0	0
T32	0	502	0	0
T41	826598	5536	0	0
T42	0	393	0	0
T45	92406	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147179235	798930	0	0
T5	182623	942	0	0
T6	121746	0	0	0
T9	20356	0	0	0
T10	216572	4114	0	0
T11	753737	8094	0	0
T12	147955	5061	0	0
T13	128925	0	0	0
T14	0	7675	0	0
T24	0	1302	0	0
T31	601887	2858	0	0
T32	0	502	0	0
T41	826598	5536	0	0
T42	0	393	0	0
T45	92406	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147179235	116716496	0	0
T1	220793	220468	0	0
T2	15148	15148	0	0
T3	2268	2268	0	0
T4	1135	0	0	0
T5	182623	181611	0	0
T6	121746	121746	0	0
T9	20356	20356	0	0
T10	216572	214511	0	0
T11	753737	751481	0	0
T12	147955	112058	0	0
T13	0	128714	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147179235	116716496	0	0
T1	220793	220468	0	0
T2	15148	15148	0	0
T3	2268	2268	0	0
T4	1135	0	0	0
T5	182623	181611	0	0
T6	121746	121746	0	0
T9	20356	20356	0	0
T10	216572	214511	0	0
T11	753737	751481	0	0
T12	147955	112058	0	0
T13	0	128714	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147179235	798930	0	0
T5	182623	942	0	0
T6	121746	0	0	0
T9	20356	0	0	0
T10	216572	4114	0	0
T11	753737	8094	0	0
T12	147955	5061	0	0
T13	128925	0	0	0
T14	0	7675	0	0
T24	0	1302	0	0
T31	601887	2858	0	0
T32	0	502	0	0
T41	826598	5536	0	0
T42	0	393	0	0
T45	92406	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147179235	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147179235	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147179235	798930	0	0
T5	182623	942	0	0
T6	121746	0	0	0
T9	20356	0	0	0
T10	216572	4114	0	0
T11	753737	8094	0	0
T12	147955	5061	0	0
T13	128925	0	0	0
T14	0	7675	0	0
T24	0	1302	0	0
T31	601887	2858	0	0
T32	0	502	0	0
T41	826598	5536	0	0
T42	0	393	0	0
T45	92406	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147179235	798930	0	0
T5	182623	942	0	0
T6	121746	0	0	0
T9	20356	0	0	0
T10	216572	4114	0	0
T11	753737	8094	0	0
T12	147955	5061	0	0
T13	128925	0	0	0
T14	0	7675	0	0
T24	0	1302	0	0
T31	601887	2858	0	0
T32	0	502	0	0
T41	826598	5536	0	0
T42	0	393	0	0
T45	92406	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147179235	798930	0	0
T5	182623	942	0	0
T6	121746	0	0	0
T9	20356	0	0	0
T10	216572	4114	0	0
T11	753737	8094	0	0
T12	147955	5061	0	0
T13	128925	0	0	0
T14	0	7675	0	0
T24	0	1302	0	0
T31	601887	2858	0	0
T32	0	502	0	0
T41	826598	5536	0	0
T42	0	393	0	0
T45	92406	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	147179235	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147179235	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147179235	116716496	0	0
T1	220793	220468	0	0
T2	15148	15148	0	0
T3	2268	2268	0	0
T4	1135	0	0	0
T5	182623	181611	0	0
T6	121746	121746	0	0
T9	20356	20356	0	0
T10	216572	214511	0	0
T11	753737	751481	0	0
T12	147955	112058	0	0
T13	0	128714	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147179235	798930	0	0
T5	182623	942	0	0
T6	121746	0	0	0
T9	20356	0	0	0
T10	216572	4114	0	0
T11	753737	8094	0	0
T12	147955	5061	0	0
T13	128925	0	0	0
T14	0	7675	0	0
T24	0	1302	0	0
T31	601887	2858	0	0
T32	0	502	0	0
T41	826598	5536	0	0
T42	0	393	0	0
T45	92406	0	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T10,T11

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T10,T11
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417231415	417144399	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	417231415	2188711	0	0
GntImpliesValid_A	417231415	2188711	0	0
GrantKnown_A	417231415	417144399	0	0
IdxKnown_A	417231415	417144399	0	0
IndexIsCorrect_A	417231415	2188711	0	0
LockArbDecision_A	417231415	0	0	0
NoReadyValidNoGrant_A	417231415	0	0	0
ReadyAndValidImplyGrant_A	417231415	2188711	0	0
ReqAndReadyImplyGrant_A	417231415	2188711	0	0
ReqImpliesValid_A	417231415	2188711	0	0
ReqStaysHighUntilGranted0_M	417231415	0	0	0
RoundRobin_A	417231415	4	0	956
ValidKnown_A	417231415	417144399	0	0
gen_data_port_assertion.DataFlow_A	417231415	2188711	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417231415	417144399	0	0
T1	154741	154733	0	0
T2	7128	7028	0	0
T3	4435	4347	0	0
T4	9814	9760	0	0
T5	148651	148642	0	0
T6	33187	33108	0	0
T7	1050	986	0	0
T8	1189	1093	0	0
T9	23171	23091	0	0
T10	901261	901189	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417231415	2188711	0	0
T1	154741	832	0	0
T2	7128	832	0	0
T3	4435	832	0	0
T4	9814	0	0	0
T5	148651	6080	0	0
T6	33187	832	0	0
T7	1050	0	0	0
T8	1189	0	0	0
T9	23171	832	0	0
T10	901261	5263	0	0
T11	0	9590	0	0
T12	0	14649	0	0
T13	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417231415	2188711	0	0
T1	154741	832	0	0
T2	7128	832	0	0
T3	4435	832	0	0
T4	9814	0	0	0
T5	148651	6080	0	0
T6	33187	832	0	0
T7	1050	0	0	0
T8	1189	0	0	0
T9	23171	832	0	0
T10	901261	5263	0	0
T11	0	9590	0	0
T12	0	14649	0	0
T13	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417231415	417144399	0	0
T1	154741	154733	0	0
T2	7128	7028	0	0
T3	4435	4347	0	0
T4	9814	9760	0	0
T5	148651	148642	0	0
T6	33187	33108	0	0
T7	1050	986	0	0
T8	1189	1093	0	0
T9	23171	23091	0	0
T10	901261	901189	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417231415	417144399	0	0
T1	154741	154733	0	0
T2	7128	7028	0	0
T3	4435	4347	0	0
T4	9814	9760	0	0
T5	148651	148642	0	0
T6	33187	33108	0	0
T7	1050	986	0	0
T8	1189	1093	0	0
T9	23171	23091	0	0
T10	901261	901189	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417231415	2188711	0	0
T1	154741	832	0	0
T2	7128	832	0	0
T3	4435	832	0	0
T4	9814	0	0	0
T5	148651	6080	0	0
T6	33187	832	0	0
T7	1050	0	0	0
T8	1189	0	0	0
T9	23171	832	0	0
T10	901261	5263	0	0
T11	0	9590	0	0
T12	0	14649	0	0
T13	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417231415	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417231415	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417231415	2188711	0	0
T1	154741	832	0	0
T2	7128	832	0	0
T3	4435	832	0	0
T4	9814	0	0	0
T5	148651	6080	0	0
T6	33187	832	0	0
T7	1050	0	0	0
T8	1189	0	0	0
T9	23171	832	0	0
T10	901261	5263	0	0
T11	0	9590	0	0
T12	0	14649	0	0
T13	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417231415	2188711	0	0
T1	154741	832	0	0
T2	7128	832	0	0
T3	4435	832	0	0
T4	9814	0	0	0
T5	148651	6080	0	0
T6	33187	832	0	0
T7	1050	0	0	0
T8	1189	0	0	0
T9	23171	832	0	0
T10	901261	5263	0	0
T11	0	9590	0	0
T12	0	14649	0	0
T13	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417231415	2188711	0	0
T1	154741	832	0	0
T2	7128	832	0	0
T3	4435	832	0	0
T4	9814	0	0	0
T5	148651	6080	0	0
T6	33187	832	0	0
T7	1050	0	0	0
T8	1189	0	0	0
T9	23171	832	0	0
T10	901261	5263	0	0
T11	0	9590	0	0
T12	0	14649	0	0
T13	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417231415	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417231415	4	0	956
T51	699869	1	0	1
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	206526	0	0	1
T56	96887	0	0	1
T57	124440	0	0	1
T58	12976	0	0	1
T59	905435	0	0	1
T60	33246	0	0	1
T61	2520	0	0	1
T62	808	0	0	1
T63	1117	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417231415	417144399	0	0
T1	154741	154733	0	0
T2	7128	7028	0	0
T3	4435	4347	0	0
T4	9814	9760	0	0
T5	148651	148642	0	0
T6	33187	33108	0	0
T7	1050	986	0	0
T8	1189	1093	0	0
T9	23171	23091	0	0
T10	901261	901189	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417231415	2188711	0	0
T1	154741	832	0	0
T2	7128	832	0	0
T3	4435	832	0	0
T4	9814	0	0	0
T5	148651	6080	0	0
T6	33187	832	0	0
T7	1050	0	0	0
T8	1189	0	0	0
T9	23171	832	0	0
T10	901261	5263	0	0
T11	0	9590	0	0
T12	0	14649	0	0
T13	0	832	0	0