Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3624121	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4221153

1

T1

887

T2

9891

T3

9898

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4347517	1			T1	4		T2	17932		T3	14519
values[0x0]	1747016	1			T1	434		T2	436		T3	1322
values[0x1]	1750741	1			T1	452		T2	448		T3	1367

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2571867	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5273407

1

T1

887

T2

11701

T3

11356

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27261	1			T3	74		T4	284		T5	4
valid_sources[0x01]	28344	1			T3	65		T4	231		T5	5
valid_sources[0x02]	27356	1			T3	55		T4	211		T5	10
valid_sources[0x03]	35057	1			T3	75		T4	187		T5	12
valid_sources[0x04]	30661	1			T3	78		T4	203		T5	7
valid_sources[0x05]	31927	1			T3	66		T4	197		T5	6
valid_sources[0x06]	29875	1			T3	49		T4	246		T5	7
valid_sources[0x07]	31850	1			T3	70		T4	184		T5	9
valid_sources[0x08]	27850	1			T3	70		T4	199		T5	9
valid_sources[0x09]	32831	1			T3	45		T4	200		T5	7
valid_sources[0x0a]	29730	1			T3	97		T4	180		T5	15
valid_sources[0x0b]	30534	1			T3	53		T4	248		T5	9
valid_sources[0x0c]	27784	1			T3	43		T4	213		T5	6
valid_sources[0x0d]	30985	1			T3	80		T4	255		T5	4
valid_sources[0x0e]	26844	1			T3	99		T4	295		T5	9
valid_sources[0x0f]	28986	1			T3	85		T4	245		T5	4
valid_sources[0x10]	34644	1			T3	87		T4	198		T5	8
valid_sources[0x11]	29711	1			T3	46		T4	247		T5	10
valid_sources[0x12]	30919	1			T3	68		T4	242		T5	6
valid_sources[0x13]	31402	1			T3	60		T4	222		T5	8
valid_sources[0x14]	27441	1			T3	86		T4	212		T5	13
valid_sources[0x15]	36891	1			T3	49		T4	217		T5	7
valid_sources[0x16]	31141	1			T3	79		T4	250		T5	7
valid_sources[0x17]	30189	1			T3	84		T4	252		T5	11
valid_sources[0x18]	30434	1			T3	61		T4	209		T5	3
valid_sources[0x19]	28396	1			T3	59		T4	225		T5	4
valid_sources[0x1a]	28778	1			T3	71		T4	211		T5	6
valid_sources[0x1b]	30777	1			T3	64		T4	212		T5	7
valid_sources[0x1c]	31232	1			T3	91		T4	237		T5	10
valid_sources[0x1d]	28265	1			T3	58		T4	258		T5	8
valid_sources[0x1e]	30176	1			T3	70		T4	270		T5	4
valid_sources[0x1f]	34724	1			T3	63		T4	201		T5	7
valid_sources[0x20]	31417	1			T3	59		T4	226		T5	7
valid_sources[0x21]	29576	1			T3	62		T4	303		T5	10
valid_sources[0x22]	29588	1			T3	69		T4	223		T5	3
valid_sources[0x23]	30216	1			T3	85		T4	155		T5	8
valid_sources[0x24]	30364	1			T3	65		T4	218		T5	5
valid_sources[0x25]	29383	1			T3	66		T4	218		T5	10
valid_sources[0x26]	29446	1			T3	61		T4	242		T5	13
valid_sources[0x27]	31047	1			T3	83		T4	260		T5	6
valid_sources[0x28]	29004	1			T3	66		T4	247		T5	7
valid_sources[0x29]	32632	1			T3	101		T4	209		T5	15
valid_sources[0x2a]	30330	1			T3	76		T4	233		T5	9
valid_sources[0x2b]	33684	1			T3	57		T4	216		T5	11
valid_sources[0x2c]	27623	1			T3	36		T4	182		T5	9
valid_sources[0x2d]	26981	1			T3	85		T4	216		T5	10
valid_sources[0x2e]	29883	1			T3	74		T4	222		T5	8
valid_sources[0x2f]	29726	1			T3	60		T4	191		T5	10
valid_sources[0x30]	28410	1			T3	47		T4	190		T5	13
valid_sources[0x31]	29459	1			T3	59		T4	340		T5	7
valid_sources[0x32]	30774	1			T3	79		T4	198		T5	5
valid_sources[0x33]	32767	1			T3	73		T4	265		T5	10
valid_sources[0x34]	27265	1			T3	52		T4	186		T5	15
valid_sources[0x35]	30707	1			T3	75		T4	187		T5	12
valid_sources[0x36]	31227	1			T3	48		T4	236		T5	6
valid_sources[0x37]	38525	1			T3	43		T4	198		T5	6
valid_sources[0x38]	29297	1			T3	88		T4	254		T5	11
valid_sources[0x39]	33495	1			T3	69		T4	218		T5	6
valid_sources[0x3a]	32412	1			T3	69		T4	179		T5	6
valid_sources[0x3b]	31242	1			T3	61		T4	216		T5	8
valid_sources[0x3c]	28232	1			T3	55		T4	205		T5	7
valid_sources[0x3d]	30552	1			T3	61		T4	230		T5	6
valid_sources[0x3e]	31206	1			T3	65		T4	222		T5	8
valid_sources[0x3f]	29050	1			T3	59		T4	254		T5	4
valid_sources[0x40]	34060	1			T3	49		T4	226		T5	5
valid_sources[0x41]	30510	1			T3	104		T4	244		T5	8
valid_sources[0x42]	31167	1			T3	71		T4	226		T5	11
valid_sources[0x43]	27067	1			T3	80		T4	245		T5	10
valid_sources[0x44]	29725	1			T3	58		T4	220		T5	9
valid_sources[0x45]	38142	1			T3	56		T4	257		T5	10
valid_sources[0x46]	29047	1			T3	68		T4	265		T5	10
valid_sources[0x47]	31451	1			T3	56		T4	297		T5	6
valid_sources[0x48]	34480	1			T3	68		T4	267		T5	3
valid_sources[0x49]	29346	1			T3	66		T4	211		T5	3
valid_sources[0x4a]	30478	1			T3	70		T4	183		T5	8
valid_sources[0x4b]	29361	1			T3	57		T4	204		T5	7
valid_sources[0x4c]	31034	1			T3	115		T4	189		T5	10
valid_sources[0x4d]	27960	1			T3	63		T4	277		T5	7
valid_sources[0x4e]	29802	1			T3	64		T4	252		T5	8
valid_sources[0x4f]	31585	1			T3	72		T4	211		T5	5
valid_sources[0x50]	30076	1			T3	55		T4	193		T5	8
valid_sources[0x51]	29790	1			T3	89		T4	214		T5	5
valid_sources[0x52]	35608	1			T3	61		T4	204		T5	7
valid_sources[0x53]	30770	1			T3	61		T4	224		T5	11
valid_sources[0x54]	30942	1			T3	87		T4	183		T5	6
valid_sources[0x55]	28627	1			T3	88		T4	290		T5	3
valid_sources[0x56]	30412	1			T3	55		T4	218		T5	5
valid_sources[0x57]	29144	1			T3	66		T4	233		T5	10
valid_sources[0x58]	31061	1			T3	39		T4	224		T5	9
valid_sources[0x59]	30168	1			T3	84		T4	200		T5	12
valid_sources[0x5a]	30472	1			T3	84		T4	188		T5	10
valid_sources[0x5b]	27129	1			T3	61		T4	160		T5	8
valid_sources[0x5c]	26632	1			T3	57		T4	197		T5	12
valid_sources[0x5d]	32549	1			T3	56		T4	202		T5	10
valid_sources[0x5e]	29920	1			T3	45		T4	208		T5	6
valid_sources[0x5f]	31588	1			T3	68		T4	228		T5	8
valid_sources[0x60]	33459	1			T3	70		T4	257		T5	10
valid_sources[0x61]	29559	1			T3	94		T4	227		T5	9
valid_sources[0x62]	30004	1			T3	56		T4	230		T5	6
valid_sources[0x63]	30614	1			T3	52		T4	249		T5	3
valid_sources[0x64]	29085	1			T3	67		T4	306		T5	8
valid_sources[0x65]	29253	1			T3	79		T4	244		T5	4
valid_sources[0x66]	32854	1			T3	61		T4	219		T5	4
valid_sources[0x67]	31785	1			T3	76		T4	213		T5	11
valid_sources[0x68]	26837	1			T3	94		T4	222		T5	4
valid_sources[0x69]	29890	1			T3	60		T4	231		T5	15
valid_sources[0x6a]	29027	1			T3	73		T4	197		T5	10
valid_sources[0x6b]	29682	1			T3	73		T4	225		T5	3
valid_sources[0x6c]	30265	1			T3	61		T4	226		T5	8
valid_sources[0x6d]	32690	1			T3	58		T4	206		T5	13
valid_sources[0x6e]	26900	1			T3	67		T4	204		T5	7
valid_sources[0x6f]	35813	1			T3	34		T4	292		T5	7
valid_sources[0x70]	28670	1			T3	48		T4	223		T5	7
valid_sources[0x71]	28805	1			T3	96		T4	234		T5	12
valid_sources[0x72]	28162	1			T3	61		T4	190		T5	9
valid_sources[0x73]	30128	1			T3	88		T4	215		T5	9
valid_sources[0x74]	31654	1			T3	90		T4	232		T5	5
valid_sources[0x75]	29710	1			T3	42		T4	226		T5	3
valid_sources[0x76]	39115	1			T3	74		T4	214		T5	6
valid_sources[0x77]	30548	1			T3	67		T4	210		T5	6
valid_sources[0x78]	29729	1			T3	69		T4	224		T5	7
valid_sources[0x79]	27108	1			T3	38		T4	157		T5	9
valid_sources[0x7a]	30866	1			T3	74		T4	146		T5	8
valid_sources[0x7b]	54500	1			T3	63		T4	258		T5	6
valid_sources[0x7c]	29075	1			T3	76		T4	209		T5	7
valid_sources[0x7d]	28696	1			T3	63		T4	282		T5	9
valid_sources[0x7e]	29435	1			T3	62		T4	201		T5	6
valid_sources[0x7f]	30090	1			T3	65		T4	197		T5	8
valid_sources[0x80]	33331	1			T3	50		T4	245		T5	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1055388

1

T1

2

T2

9013

T3

7222

values[0x0]

all_enables

biggest_size

1593611

1

T1

433

T2

436

T3

1317

values[0x1]

all_enables

biggest_size

1572154

1

T1

452

T2

442

T3

1359