Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3642340

1

T1

3

T2

8925

T3

7310

full_word

4222251

1

T1

887

T2

9891

T3

9898

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7864091	1			T1	890		T2	18816		T3	17208
auto[TlIntgErrCmd]	167	1			T62	5		T81	7		T82	4
auto[TlIntgErrData]	158	1			T62	7		T81	7		T82	6
auto[TlIntgErrBoth]	175	1			T62	8		T81	6		T82	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4350203

1

T1

4

T2

17932

T3

14519

auto[1]

3514388

1

T1

886

T2

884

T3

2689

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3294399	1			T1	2		T2	8919		T3	7297
auto[TlIntgErrNone]	partial	auto[1]	347497	1			T1	1		T2	6		T3	13
auto[TlIntgErrNone]	full_word	auto[0]	1055581	1			T1	2		T2	9013		T3	7222
auto[TlIntgErrNone]	full_word	auto[1]	3166614	1			T1	885		T2	878		T3	2676
auto[TlIntgErrCmd]	partial	auto[0]	68	1			T62	3		T81	2		T82	2
auto[TlIntgErrCmd]	partial	auto[1]	86	1			T62	1		T81	5		T82	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T162	1		T163	1		T90	1
auto[TlIntgErrCmd]	full_word	auto[1]	10	1			T62	1		T162	1		T160	1
auto[TlIntgErrData]	partial	auto[0]	67	1			T62	3		T81	1		T82	3
auto[TlIntgErrData]	partial	auto[1]	67	1			T62	2		T81	3		T82	3
auto[TlIntgErrData]	full_word	auto[0]	16	1			T62	1		T81	2		T160	2
auto[TlIntgErrData]	full_word	auto[1]	8	1			T62	1		T81	1		T161	1
auto[TlIntgErrBoth]	partial	auto[0]	60	1			T62	3		T81	1		T82	3
auto[TlIntgErrBoth]	partial	auto[1]	96	1			T62	5		T81	4		T82	6
auto[TlIntgErrBoth]	full_word	auto[0]	9	1			T81	1		T162	3		T157	1
auto[TlIntgErrBoth]	full_word	auto[1]	10	1			T82	1		T162	1		T157	1