Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	457926760	2809543	0	0
DepthKnown_A	457926760	457790361	0	0
RvalidKnown_A	457926760	457790361	0	0
WreadyKnown_A	457926760	457790361	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457926760	2809543	0	0
T1	120502	1663	0	0
T2	399218	1663	0	0
T3	587883	5240	0	0
T4	225871	18296	0	0
T5	88550	1663	0	0
T6	944889	6653	0	0
T7	579461	1672	0	0
T8	136433	832	0	0
T9	3552	0	0	0
T10	789	0	0	0
T11	0	1663	0	0
T13	0	1663	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457926760	457790361	0	0
T1	120502	120449	0	0
T2	399218	399123	0	0
T3	587883	587828	0	0
T4	225871	225863	0	0
T5	88550	88475	0	0
T6	944889	944827	0	0
T7	579461	579393	0	0
T8	136433	136345	0	0
T9	3552	2699	0	0
T10	789	733	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457926760	457790361	0	0
T1	120502	120449	0	0
T2	399218	399123	0	0
T3	587883	587828	0	0
T4	225871	225863	0	0
T5	88550	88475	0	0
T6	944889	944827	0	0
T7	579461	579393	0	0
T8	136433	136345	0	0
T9	3552	2699	0	0
T10	789	733	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457926760	457790361	0	0
T1	120502	120449	0	0
T2	399218	399123	0	0
T3	587883	587828	0	0
T4	225871	225863	0	0
T5	88550	88475	0	0
T6	944889	944827	0	0
T7	579461	579393	0	0
T8	136433	136345	0	0
T9	3552	2699	0	0
T10	789	733	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	457926760	3062069	0	0
DepthKnown_A	457926760	457790361	0	0
RvalidKnown_A	457926760	457790361	0	0
WreadyKnown_A	457926760	457790361	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457926760	3062069	0	0
T1	120502	832	0	0
T2	399218	832	0	0
T3	587883	2624	0	0
T4	225871	11648	0	0
T5	88550	832	0	0
T6	944889	4160	0	0
T7	579461	841	0	0
T8	136433	832	0	0
T9	3552	0	0	0
T10	789	0	0	0
T11	0	832	0	0
T13	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457926760	457790361	0	0
T1	120502	120449	0	0
T2	399218	399123	0	0
T3	587883	587828	0	0
T4	225871	225863	0	0
T5	88550	88475	0	0
T6	944889	944827	0	0
T7	579461	579393	0	0
T8	136433	136345	0	0
T9	3552	2699	0	0
T10	789	733	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457926760	457790361	0	0
T1	120502	120449	0	0
T2	399218	399123	0	0
T3	587883	587828	0	0
T4	225871	225863	0	0
T5	88550	88475	0	0
T6	944889	944827	0	0
T7	579461	579393	0	0
T8	136433	136345	0	0
T9	3552	2699	0	0
T10	789	733	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457926760	457790361	0	0
T1	120502	120449	0	0
T2	399218	399123	0	0
T3	587883	587828	0	0
T4	225871	225863	0	0
T5	88550	88475	0	0
T6	944889	944827	0	0
T7	579461	579393	0	0
T8	136433	136345	0	0
T9	3552	2699	0	0
T10	789	733	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	457926760	181693	0	0
DepthKnown_A	457926760	457790361	0	0
RvalidKnown_A	457926760	457790361	0	0
WreadyKnown_A	457926760	457790361	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457926760	181693	0	0
T4	225871	1338	0	0
T5	88550	0	0	0
T6	944889	87	0	0
T7	579461	66	0	0
T8	136433	0	0	0
T9	3552	0	0	0
T10	789	0	0	0
T11	8079	0	0	0
T12	2607	0	0	0
T13	0	2	0	0
T23	1147	0	0	0
T24	0	227	0	0
T27	0	131	0	0
T28	0	674	0	0
T29	0	707	0	0
T33	0	234	0	0
T36	0	358	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457926760	457790361	0	0
T1	120502	120449	0	0
T2	399218	399123	0	0
T3	587883	587828	0	0
T4	225871	225863	0	0
T5	88550	88475	0	0
T6	944889	944827	0	0
T7	579461	579393	0	0
T8	136433	136345	0	0
T9	3552	2699	0	0
T10	789	733	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457926760	457790361	0	0
T1	120502	120449	0	0
T2	399218	399123	0	0
T3	587883	587828	0	0
T4	225871	225863	0	0
T5	88550	88475	0	0
T6	944889	944827	0	0
T7	579461	579393	0	0
T8	136433	136345	0	0
T9	3552	2699	0	0
T10	789	733	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457926760	457790361	0	0
T1	120502	120449	0	0
T2	399218	399123	0	0
T3	587883	587828	0	0
T4	225871	225863	0	0
T5	88550	88475	0	0
T6	944889	944827	0	0
T7	579461	579393	0	0
T8	136433	136345	0	0
T9	3552	2699	0	0
T10	789	733	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	457926760	392698	0	0
DepthKnown_A	457926760	457790361	0	0
RvalidKnown_A	457926760	457790361	0	0
WreadyKnown_A	457926760	457790361	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457926760	392698	0	0
T4	225871	1337	0	0
T5	88550	0	0	0
T6	944889	87	0	0
T7	579461	297	0	0
T8	136433	0	0	0
T9	3552	0	0	0
T10	789	0	0	0
T11	8079	0	0	0
T12	2607	0	0	0
T13	0	2	0	0
T23	1147	0	0	0
T24	0	980	0	0
T27	0	579	0	0
T28	0	674	0	0
T29	0	707	0	0
T33	0	741	0	0
T36	0	358	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457926760	457790361	0	0
T1	120502	120449	0	0
T2	399218	399123	0	0
T3	587883	587828	0	0
T4	225871	225863	0	0
T5	88550	88475	0	0
T6	944889	944827	0	0
T7	579461	579393	0	0
T8	136433	136345	0	0
T9	3552	2699	0	0
T10	789	733	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457926760	457790361	0	0
T1	120502	120449	0	0
T2	399218	399123	0	0
T3	587883	587828	0	0
T4	225871	225863	0	0
T5	88550	88475	0	0
T6	944889	944827	0	0
T7	579461	579393	0	0
T8	136433	136345	0	0
T9	3552	2699	0	0
T10	789	733	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457926760	457790361	0	0
T1	120502	120449	0	0
T2	399218	399123	0	0
T3	587883	587828	0	0
T4	225871	225863	0	0
T5	88550	88475	0	0
T6	944889	944827	0	0
T7	579461	579393	0	0
T8	136433	136345	0	0
T9	3552	2699	0	0
T10	789	733	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	457926760	6267459	0	0
DepthKnown_A	457926760	457790361	0	0
RvalidKnown_A	457926760	457790361	0	0
WreadyKnown_A	457926760	457790361	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457926760	6267459	0	0
T1	120502	58	0	0
T2	399218	17984	0	0
T3	587883	14585	0	0
T4	225871	44775	0	0
T5	88550	1272	0	0
T6	944889	5530	0	0
T7	579461	928	0	0
T8	136433	269	0	0
T9	3552	1	0	0
T10	789	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457926760	457790361	0	0
T1	120502	120449	0	0
T2	399218	399123	0	0
T3	587883	587828	0	0
T4	225871	225863	0	0
T5	88550	88475	0	0
T6	944889	944827	0	0
T7	579461	579393	0	0
T8	136433	136345	0	0
T9	3552	2699	0	0
T10	789	733	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457926760	457790361	0	0
T1	120502	120449	0	0
T2	399218	399123	0	0
T3	587883	587828	0	0
T4	225871	225863	0	0
T5	88550	88475	0	0
T6	944889	944827	0	0
T7	579461	579393	0	0
T8	136433	136345	0	0
T9	3552	2699	0	0
T10	789	733	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457926760	457790361	0	0
T1	120502	120449	0	0
T2	399218	399123	0	0
T3	587883	587828	0	0
T4	225871	225863	0	0
T5	88550	88475	0	0
T6	944889	944827	0	0
T7	579461	579393	0	0
T8	136433	136345	0	0
T9	3552	2699	0	0
T10	789	733	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	457926760	12254406	0	0
DepthKnown_A	457926760	457790361	0	0
RvalidKnown_A	457926760	457790361	0	0
WreadyKnown_A	457926760	457790361	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457926760	12254406	0	0
T1	120502	165	0	0
T2	399218	17984	0	0
T3	587883	14584	0	0
T4	225871	44484	0	0
T5	88550	1272	0	0
T6	944889	5495	0	0
T7	579461	3882	0	0
T8	136433	268	0	0
T9	3552	1	0	0
T10	789	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457926760	457790361	0	0
T1	120502	120449	0	0
T2	399218	399123	0	0
T3	587883	587828	0	0
T4	225871	225863	0	0
T5	88550	88475	0	0
T6	944889	944827	0	0
T7	579461	579393	0	0
T8	136433	136345	0	0
T9	3552	2699	0	0
T10	789	733	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457926760	457790361	0	0
T1	120502	120449	0	0
T2	399218	399123	0	0
T3	587883	587828	0	0
T4	225871	225863	0	0
T5	88550	88475	0	0
T6	944889	944827	0	0
T7	579461	579393	0	0
T8	136433	136345	0	0
T9	3552	2699	0	0
T10	789	733	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457926760	457790361	0	0
T1	120502	120449	0	0
T2	399218	399123	0	0
T3	587883	587828	0	0
T4	225871	225863	0	0
T5	88550	88475	0	0
T6	944889	944827	0	0
T7	579461	579393	0	0
T8	136433	136345	0	0
T9	3552	2699	0	0
T10	789	733	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0