Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T24
1	0	Covered	T4,T6,T24

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T12
1	0	Unreachable
1	1	Covered	T4,T6,T24

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T6,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T4,T6,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	751047753	601820022	0	0
CheckNGreaterZero_A	2868	2868	0	0
GntImpliesReady_A	751047753	3707007	0	0
GntImpliesValid_A	751047753	3707007	0	0
GrantKnown_A	751047753	601820022	0	0
IdxKnown_A	751047753	601820022	0	0
IndexIsCorrect_A	751047753	3707007	0	0
LockArbDecision_A	751047753	0	0	0
NoReadyValidNoGrant_A	751047753	0	0	0
ReadyAndValidImplyGrant_A	751047753	3707007	0	0
ReqAndReadyImplyGrant_A	751047753	3707007	0	0
ReqImpliesValid_A	751047753	3707007	0	0
ReqStaysHighUntilGranted0_M	751047753	0	0	0
RoundRobin_A	751047753	3	0	956
ValidKnown_A	751047753	601820022	0	0
gen_data_port_assertion.DataFlow_A	751047753	3707007	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751047753	601820022	0	0
T1	149772	149719	0	0
T2	465210	465115	0	0
T3	705342	704379	0	0
T4	1730203	963847	0	0
T5	123822	105363	0	0
T6	1318589	1129735	0	0
T7	769969	674345	0	0
T8	203341	169551	0	0
T9	3552	2699	0	0
T10	789	733	0	0
T11	18052	9026	0	0
T12	1762	864	0	0
T13	131226	131226	0	0
T24	35156	34784	0	0
T25	1125	720	0	0
T28	0	290632	0	0
T29	0	27000	0	0
T30	0	648	0	0
T33	0	160496	0	0
T34	0	28928	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2868	2868	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751047753	3707007	0	0
T1	120502	832	0	0
T2	399218	832	0	0
T3	587883	2624	0	0
T4	1730203	25205	0	0
T5	123822	832	0	0
T6	1318589	4670	0	0
T7	769969	1180	0	0
T8	203341	832	0	0
T9	3552	0	0	0
T10	789	0	0	0
T11	18052	832	0	0
T12	1762	0	0	0
T13	262452	10	0	0
T24	70312	2044	0	0
T25	2250	0	0	0
T27	0	3251	0	0
T28	0	5842	0	0
T29	0	10777	0	0
T33	0	1589	0	0
T36	0	1458	0	0
T43	0	5845	0	0
T44	0	3076	0	0
T45	0	188	0	0
T46	0	32	0	0
T47	0	258	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751047753	3707007	0	0
T1	120502	832	0	0
T2	399218	832	0	0
T3	587883	2624	0	0
T4	1730203	25205	0	0
T5	123822	832	0	0
T6	1318589	4670	0	0
T7	769969	1180	0	0
T8	203341	832	0	0
T9	3552	0	0	0
T10	789	0	0	0
T11	18052	832	0	0
T12	1762	0	0	0
T13	262452	10	0	0
T24	70312	2044	0	0
T25	2250	0	0	0
T27	0	3251	0	0
T28	0	5842	0	0
T29	0	10777	0	0
T33	0	1589	0	0
T36	0	1458	0	0
T43	0	5845	0	0
T44	0	3076	0	0
T45	0	188	0	0
T46	0	32	0	0
T47	0	258	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751047753	601820022	0	0
T1	149772	149719	0	0
T2	465210	465115	0	0
T3	705342	704379	0	0
T4	1730203	963847	0	0
T5	123822	105363	0	0
T6	1318589	1129735	0	0
T7	769969	674345	0	0
T8	203341	169551	0	0
T9	3552	2699	0	0
T10	789	733	0	0
T11	18052	9026	0	0
T12	1762	864	0	0
T13	131226	131226	0	0
T24	35156	34784	0	0
T25	1125	720	0	0
T28	0	290632	0	0
T29	0	27000	0	0
T30	0	648	0	0
T33	0	160496	0	0
T34	0	28928	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751047753	601820022	0	0
T1	149772	149719	0	0
T2	465210	465115	0	0
T3	705342	704379	0	0
T4	1730203	963847	0	0
T5	123822	105363	0	0
T6	1318589	1129735	0	0
T7	769969	674345	0	0
T8	203341	169551	0	0
T9	3552	2699	0	0
T10	789	733	0	0
T11	18052	9026	0	0
T12	1762	864	0	0
T13	131226	131226	0	0
T24	35156	34784	0	0
T25	1125	720	0	0
T28	0	290632	0	0
T29	0	27000	0	0
T30	0	648	0	0
T33	0	160496	0	0
T34	0	28928	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751047753	3707007	0	0
T1	120502	832	0	0
T2	399218	832	0	0
T3	587883	2624	0	0
T4	1730203	25205	0	0
T5	123822	832	0	0
T6	1318589	4670	0	0
T7	769969	1180	0	0
T8	203341	832	0	0
T9	3552	0	0	0
T10	789	0	0	0
T11	18052	832	0	0
T12	1762	0	0	0
T13	262452	10	0	0
T24	70312	2044	0	0
T25	2250	0	0	0
T27	0	3251	0	0
T28	0	5842	0	0
T29	0	10777	0	0
T33	0	1589	0	0
T36	0	1458	0	0
T43	0	5845	0	0
T44	0	3076	0	0
T45	0	188	0	0
T46	0	32	0	0
T47	0	258	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751047753	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751047753	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751047753	3707007	0	0
T1	120502	832	0	0
T2	399218	832	0	0
T3	587883	2624	0	0
T4	1730203	25205	0	0
T5	123822	832	0	0
T6	1318589	4670	0	0
T7	769969	1180	0	0
T8	203341	832	0	0
T9	3552	0	0	0
T10	789	0	0	0
T11	18052	832	0	0
T12	1762	0	0	0
T13	262452	10	0	0
T24	70312	2044	0	0
T25	2250	0	0	0
T27	0	3251	0	0
T28	0	5842	0	0
T29	0	10777	0	0
T33	0	1589	0	0
T36	0	1458	0	0
T43	0	5845	0	0
T44	0	3076	0	0
T45	0	188	0	0
T46	0	32	0	0
T47	0	258	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751047753	3707007	0	0
T1	120502	832	0	0
T2	399218	832	0	0
T3	587883	2624	0	0
T4	1730203	25205	0	0
T5	123822	832	0	0
T6	1318589	4670	0	0
T7	769969	1180	0	0
T8	203341	832	0	0
T9	3552	0	0	0
T10	789	0	0	0
T11	18052	832	0	0
T12	1762	0	0	0
T13	262452	10	0	0
T24	70312	2044	0	0
T25	2250	0	0	0
T27	0	3251	0	0
T28	0	5842	0	0
T29	0	10777	0	0
T33	0	1589	0	0
T36	0	1458	0	0
T43	0	5845	0	0
T44	0	3076	0	0
T45	0	188	0	0
T46	0	32	0	0
T47	0	258	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751047753	3707007	0	0
T1	120502	832	0	0
T2	399218	832	0	0
T3	587883	2624	0	0
T4	1730203	25205	0	0
T5	123822	832	0	0
T6	1318589	4670	0	0
T7	769969	1180	0	0
T8	203341	832	0	0
T9	3552	0	0	0
T10	789	0	0	0
T11	18052	832	0	0
T12	1762	0	0	0
T13	262452	10	0	0
T24	70312	2044	0	0
T25	2250	0	0	0
T27	0	3251	0	0
T28	0	5842	0	0
T29	0	10777	0	0
T33	0	1589	0	0
T36	0	1458	0	0
T43	0	5845	0	0
T44	0	3076	0	0
T45	0	188	0	0
T46	0	32	0	0
T47	0	258	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	751047753	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751047753	3	0	956
T20	556660	1	0	1
T48	829653	1	0	1
T49	0	1	0	0
T50	46875	0	0	1
T51	18198	0	0	1
T52	1314	0	0	1
T53	631381	0	0	1
T54	77939	0	0	1
T55	53465	0	0	1
T56	26604	0	0	1
T57	18792	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751047753	601820022	0	0
T1	149772	149719	0	0
T2	465210	465115	0	0
T3	705342	704379	0	0
T4	1730203	963847	0	0
T5	123822	105363	0	0
T6	1318589	1129735	0	0
T7	769969	674345	0	0
T8	203341	169551	0	0
T9	3552	2699	0	0
T10	789	733	0	0
T11	18052	9026	0	0
T12	1762	864	0	0
T13	131226	131226	0	0
T24	35156	34784	0	0
T25	1125	720	0	0
T28	0	290632	0	0
T29	0	27000	0	0
T30	0	648	0	0
T33	0	160496	0	0
T34	0	28928	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751047753	3707007	0	0
T1	120502	832	0	0
T2	399218	832	0	0
T3	587883	2624	0	0
T4	1730203	25205	0	0
T5	123822	832	0	0
T6	1318589	4670	0	0
T7	769969	1180	0	0
T8	203341	832	0	0
T9	3552	0	0	0
T10	789	0	0	0
T11	18052	832	0	0
T12	1762	0	0	0
T13	262452	10	0	0
T24	70312	2044	0	0
T25	2250	0	0	0
T27	0	3251	0	0
T28	0	5842	0	0
T29	0	10777	0	0
T33	0	1589	0	0
T36	0	1458	0	0
T43	0	5845	0	0
T44	0	3076	0	0
T45	0	188	0	0
T46	0	32	0	0
T47	0	258	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T24
1	0	Covered	T4,T6,T24

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T12
1	0	Unreachable
1	1	Covered	T4,T6,T24

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T6,T24
0	0	1	Unreachable
0	0	0	Covered	T4,T6,T12

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T24
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T24
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	147777566	28160291	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	147777566	638926	0	0
GntImpliesValid_A	147777566	638926	0	0
GrantKnown_A	147777566	28160291	0	0
IdxKnown_A	147777566	28160291	0	0
IndexIsCorrect_A	147777566	638926	0	0
LockArbDecision_A	147777566	0	0	0
NoReadyValidNoGrant_A	147777566	0	0	0
ReadyAndValidImplyGrant_A	147777566	638926	0	0
ReqAndReadyImplyGrant_A	147777566	638926	0	0
ReqImpliesValid_A	147777566	638926	0	0
ReqStaysHighUntilGranted0_M	147777566	0	0	0
RoundRobin_A	147777566	0	0	0
ValidKnown_A	147777566	28160291	0	0
gen_data_port_assertion.DataFlow_A	147777566	638926	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147777566	28160291	0	0
T4	752166	129592	0	0
T5	17636	0	0	0
T6	186850	6768	0	0
T7	95254	0	0	0
T8	33454	0	0	0
T11	9026	0	0	0
T12	881	864	0	0
T13	131226	0	0	0
T24	35156	34784	0	0
T25	1125	720	0	0
T28	0	290632	0	0
T29	0	27000	0	0
T30	0	648	0	0
T33	0	160496	0	0
T34	0	28928	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147777566	638926	0	0
T4	752166	5081	0	0
T5	17636	0	0	0
T6	186850	327	0	0
T7	95254	0	0	0
T8	33454	0	0	0
T11	9026	0	0	0
T12	881	0	0	0
T13	131226	0	0	0
T24	35156	1368	0	0
T25	1125	0	0	0
T28	0	2688	0	0
T29	0	1135	0	0
T33	0	1589	0	0
T43	0	3073	0	0
T44	0	3076	0	0
T45	0	188	0	0
T46	0	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147777566	638926	0	0
T4	752166	5081	0	0
T5	17636	0	0	0
T6	186850	327	0	0
T7	95254	0	0	0
T8	33454	0	0	0
T11	9026	0	0	0
T12	881	0	0	0
T13	131226	0	0	0
T24	35156	1368	0	0
T25	1125	0	0	0
T28	0	2688	0	0
T29	0	1135	0	0
T33	0	1589	0	0
T43	0	3073	0	0
T44	0	3076	0	0
T45	0	188	0	0
T46	0	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147777566	28160291	0	0
T4	752166	129592	0	0
T5	17636	0	0	0
T6	186850	6768	0	0
T7	95254	0	0	0
T8	33454	0	0	0
T11	9026	0	0	0
T12	881	864	0	0
T13	131226	0	0	0
T24	35156	34784	0	0
T25	1125	720	0	0
T28	0	290632	0	0
T29	0	27000	0	0
T30	0	648	0	0
T33	0	160496	0	0
T34	0	28928	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147777566	28160291	0	0
T4	752166	129592	0	0
T5	17636	0	0	0
T6	186850	6768	0	0
T7	95254	0	0	0
T8	33454	0	0	0
T11	9026	0	0	0
T12	881	864	0	0
T13	131226	0	0	0
T24	35156	34784	0	0
T25	1125	720	0	0
T28	0	290632	0	0
T29	0	27000	0	0
T30	0	648	0	0
T33	0	160496	0	0
T34	0	28928	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147777566	638926	0	0
T4	752166	5081	0	0
T5	17636	0	0	0
T6	186850	327	0	0
T7	95254	0	0	0
T8	33454	0	0	0
T11	9026	0	0	0
T12	881	0	0	0
T13	131226	0	0	0
T24	35156	1368	0	0
T25	1125	0	0	0
T28	0	2688	0	0
T29	0	1135	0	0
T33	0	1589	0	0
T43	0	3073	0	0
T44	0	3076	0	0
T45	0	188	0	0
T46	0	32	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147777566	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147777566	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147777566	638926	0	0
T4	752166	5081	0	0
T5	17636	0	0	0
T6	186850	327	0	0
T7	95254	0	0	0
T8	33454	0	0	0
T11	9026	0	0	0
T12	881	0	0	0
T13	131226	0	0	0
T24	35156	1368	0	0
T25	1125	0	0	0
T28	0	2688	0	0
T29	0	1135	0	0
T33	0	1589	0	0
T43	0	3073	0	0
T44	0	3076	0	0
T45	0	188	0	0
T46	0	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147777566	638926	0	0
T4	752166	5081	0	0
T5	17636	0	0	0
T6	186850	327	0	0
T7	95254	0	0	0
T8	33454	0	0	0
T11	9026	0	0	0
T12	881	0	0	0
T13	131226	0	0	0
T24	35156	1368	0	0
T25	1125	0	0	0
T28	0	2688	0	0
T29	0	1135	0	0
T33	0	1589	0	0
T43	0	3073	0	0
T44	0	3076	0	0
T45	0	188	0	0
T46	0	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147777566	638926	0	0
T4	752166	5081	0	0
T5	17636	0	0	0
T6	186850	327	0	0
T7	95254	0	0	0
T8	33454	0	0	0
T11	9026	0	0	0
T12	881	0	0	0
T13	131226	0	0	0
T24	35156	1368	0	0
T25	1125	0	0	0
T28	0	2688	0	0
T29	0	1135	0	0
T33	0	1589	0	0
T43	0	3073	0	0
T44	0	3076	0	0
T45	0	188	0	0
T46	0	32	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	147777566	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147777566	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147777566	28160291	0	0
T4	752166	129592	0	0
T5	17636	0	0	0
T6	186850	6768	0	0
T7	95254	0	0	0
T8	33454	0	0	0
T11	9026	0	0	0
T12	881	864	0	0
T13	131226	0	0	0
T24	35156	34784	0	0
T25	1125	720	0	0
T28	0	290632	0	0
T29	0	27000	0	0
T30	0	648	0	0
T33	0	160496	0	0
T34	0	28928	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147777566	638926	0	0
T4	752166	5081	0	0
T5	17636	0	0	0
T6	186850	327	0	0
T7	95254	0	0	0
T8	33454	0	0	0
T11	9026	0	0	0
T12	881	0	0	0
T13	131226	0	0	0
T24	35156	1368	0	0
T25	1125	0	0	0
T28	0	2688	0	0
T29	0	1135	0	0
T33	0	1589	0	0
T43	0	3073	0	0
T44	0	3076	0	0
T45	0	188	0	0
T46	0	32	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T6,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T4,T6,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T6,T7
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	147777566	118251902	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	147777566	844534	0	0
GntImpliesValid_A	147777566	844534	0	0
GrantKnown_A	147777566	118251902	0	0
IdxKnown_A	147777566	118251902	0	0
IndexIsCorrect_A	147777566	844534	0	0
LockArbDecision_A	147777566	0	0	0
NoReadyValidNoGrant_A	147777566	0	0	0
ReadyAndValidImplyGrant_A	147777566	844534	0	0
ReqAndReadyImplyGrant_A	147777566	844534	0	0
ReqImpliesValid_A	147777566	844534	0	0
ReqStaysHighUntilGranted0_M	147777566	0	0	0
RoundRobin_A	147777566	0	0	0
ValidKnown_A	147777566	118251902	0	0
gen_data_port_assertion.DataFlow_A	147777566	844534	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147777566	118251902	0	0
T1	29270	29270	0	0
T2	65992	65992	0	0
T3	117459	116551	0	0
T4	752166	608392	0	0
T5	17636	16888	0	0
T6	186850	178140	0	0
T7	95254	94952	0	0
T8	33454	33206	0	0
T11	9026	9026	0	0
T12	881	0	0	0
T13	0	131226	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147777566	844534	0	0
T4	752166	5752	0	0
T5	17636	0	0	0
T6	186850	53	0	0
T7	95254	274	0	0
T8	33454	0	0	0
T11	9026	0	0	0
T12	881	0	0	0
T13	131226	10	0	0
T24	35156	0	0	0
T25	1125	0	0	0
T27	0	3251	0	0
T28	0	3154	0	0
T29	0	9642	0	0
T36	0	1458	0	0
T43	0	2772	0	0
T47	0	258	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147777566	844534	0	0
T4	752166	5752	0	0
T5	17636	0	0	0
T6	186850	53	0	0
T7	95254	274	0	0
T8	33454	0	0	0
T11	9026	0	0	0
T12	881	0	0	0
T13	131226	10	0	0
T24	35156	0	0	0
T25	1125	0	0	0
T27	0	3251	0	0
T28	0	3154	0	0
T29	0	9642	0	0
T36	0	1458	0	0
T43	0	2772	0	0
T47	0	258	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147777566	118251902	0	0
T1	29270	29270	0	0
T2	65992	65992	0	0
T3	117459	116551	0	0
T4	752166	608392	0	0
T5	17636	16888	0	0
T6	186850	178140	0	0
T7	95254	94952	0	0
T8	33454	33206	0	0
T11	9026	9026	0	0
T12	881	0	0	0
T13	0	131226	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147777566	118251902	0	0
T1	29270	29270	0	0
T2	65992	65992	0	0
T3	117459	116551	0	0
T4	752166	608392	0	0
T5	17636	16888	0	0
T6	186850	178140	0	0
T7	95254	94952	0	0
T8	33454	33206	0	0
T11	9026	9026	0	0
T12	881	0	0	0
T13	0	131226	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147777566	844534	0	0
T4	752166	5752	0	0
T5	17636	0	0	0
T6	186850	53	0	0
T7	95254	274	0	0
T8	33454	0	0	0
T11	9026	0	0	0
T12	881	0	0	0
T13	131226	10	0	0
T24	35156	0	0	0
T25	1125	0	0	0
T27	0	3251	0	0
T28	0	3154	0	0
T29	0	9642	0	0
T36	0	1458	0	0
T43	0	2772	0	0
T47	0	258	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147777566	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147777566	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147777566	844534	0	0
T4	752166	5752	0	0
T5	17636	0	0	0
T6	186850	53	0	0
T7	95254	274	0	0
T8	33454	0	0	0
T11	9026	0	0	0
T12	881	0	0	0
T13	131226	10	0	0
T24	35156	0	0	0
T25	1125	0	0	0
T27	0	3251	0	0
T28	0	3154	0	0
T29	0	9642	0	0
T36	0	1458	0	0
T43	0	2772	0	0
T47	0	258	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147777566	844534	0	0
T4	752166	5752	0	0
T5	17636	0	0	0
T6	186850	53	0	0
T7	95254	274	0	0
T8	33454	0	0	0
T11	9026	0	0	0
T12	881	0	0	0
T13	131226	10	0	0
T24	35156	0	0	0
T25	1125	0	0	0
T27	0	3251	0	0
T28	0	3154	0	0
T29	0	9642	0	0
T36	0	1458	0	0
T43	0	2772	0	0
T47	0	258	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147777566	844534	0	0
T4	752166	5752	0	0
T5	17636	0	0	0
T6	186850	53	0	0
T7	95254	274	0	0
T8	33454	0	0	0
T11	9026	0	0	0
T12	881	0	0	0
T13	131226	10	0	0
T24	35156	0	0	0
T25	1125	0	0	0
T27	0	3251	0	0
T28	0	3154	0	0
T29	0	9642	0	0
T36	0	1458	0	0
T43	0	2772	0	0
T47	0	258	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	147777566	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147777566	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147777566	118251902	0	0
T1	29270	29270	0	0
T2	65992	65992	0	0
T3	117459	116551	0	0
T4	752166	608392	0	0
T5	17636	16888	0	0
T6	186850	178140	0	0
T7	95254	94952	0	0
T8	33454	33206	0	0
T11	9026	9026	0	0
T12	881	0	0	0
T13	0	131226	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147777566	844534	0	0
T4	752166	5752	0	0
T5	17636	0	0	0
T6	186850	53	0	0
T7	95254	274	0	0
T8	33454	0	0	0
T11	9026	0	0	0
T12	881	0	0	0
T13	131226	10	0	0
T24	35156	0	0	0
T25	1125	0	0	0
T27	0	3251	0	0
T28	0	3154	0	0
T29	0	9642	0	0
T36	0	1458	0	0
T43	0	2772	0	0
T47	0	258	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	455492621	455407829	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	455492621	2223547	0	0
GntImpliesValid_A	455492621	2223547	0	0
GrantKnown_A	455492621	455407829	0	0
IdxKnown_A	455492621	455407829	0	0
IndexIsCorrect_A	455492621	2223547	0	0
LockArbDecision_A	455492621	0	0	0
NoReadyValidNoGrant_A	455492621	0	0	0
ReadyAndValidImplyGrant_A	455492621	2223547	0	0
ReqAndReadyImplyGrant_A	455492621	2223547	0	0
ReqImpliesValid_A	455492621	2223547	0	0
ReqStaysHighUntilGranted0_M	455492621	0	0	0
RoundRobin_A	455492621	3	0	956
ValidKnown_A	455492621	455407829	0	0
gen_data_port_assertion.DataFlow_A	455492621	2223547	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492621	455407829	0	0
T1	120502	120449	0	0
T2	399218	399123	0	0
T3	587883	587828	0	0
T4	225871	225863	0	0
T5	88550	88475	0	0
T6	944889	944827	0	0
T7	579461	579393	0	0
T8	136433	136345	0	0
T9	3552	2699	0	0
T10	789	733	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492621	2223547	0	0
T1	120502	832	0	0
T2	399218	832	0	0
T3	587883	2624	0	0
T4	225871	14372	0	0
T5	88550	832	0	0
T6	944889	4290	0	0
T7	579461	906	0	0
T8	136433	832	0	0
T9	3552	0	0	0
T10	789	0	0	0
T11	0	832	0	0
T24	0	676	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492621	2223547	0	0
T1	120502	832	0	0
T2	399218	832	0	0
T3	587883	2624	0	0
T4	225871	14372	0	0
T5	88550	832	0	0
T6	944889	4290	0	0
T7	579461	906	0	0
T8	136433	832	0	0
T9	3552	0	0	0
T10	789	0	0	0
T11	0	832	0	0
T24	0	676	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492621	455407829	0	0
T1	120502	120449	0	0
T2	399218	399123	0	0
T3	587883	587828	0	0
T4	225871	225863	0	0
T5	88550	88475	0	0
T6	944889	944827	0	0
T7	579461	579393	0	0
T8	136433	136345	0	0
T9	3552	2699	0	0
T10	789	733	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492621	455407829	0	0
T1	120502	120449	0	0
T2	399218	399123	0	0
T3	587883	587828	0	0
T4	225871	225863	0	0
T5	88550	88475	0	0
T6	944889	944827	0	0
T7	579461	579393	0	0
T8	136433	136345	0	0
T9	3552	2699	0	0
T10	789	733	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492621	2223547	0	0
T1	120502	832	0	0
T2	399218	832	0	0
T3	587883	2624	0	0
T4	225871	14372	0	0
T5	88550	832	0	0
T6	944889	4290	0	0
T7	579461	906	0	0
T8	136433	832	0	0
T9	3552	0	0	0
T10	789	0	0	0
T11	0	832	0	0
T24	0	676	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492621	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492621	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492621	2223547	0	0
T1	120502	832	0	0
T2	399218	832	0	0
T3	587883	2624	0	0
T4	225871	14372	0	0
T5	88550	832	0	0
T6	944889	4290	0	0
T7	579461	906	0	0
T8	136433	832	0	0
T9	3552	0	0	0
T10	789	0	0	0
T11	0	832	0	0
T24	0	676	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492621	2223547	0	0
T1	120502	832	0	0
T2	399218	832	0	0
T3	587883	2624	0	0
T4	225871	14372	0	0
T5	88550	832	0	0
T6	944889	4290	0	0
T7	579461	906	0	0
T8	136433	832	0	0
T9	3552	0	0	0
T10	789	0	0	0
T11	0	832	0	0
T24	0	676	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492621	2223547	0	0
T1	120502	832	0	0
T2	399218	832	0	0
T3	587883	2624	0	0
T4	225871	14372	0	0
T5	88550	832	0	0
T6	944889	4290	0	0
T7	579461	906	0	0
T8	136433	832	0	0
T9	3552	0	0	0
T10	789	0	0	0
T11	0	832	0	0
T24	0	676	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492621	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492621	3	0	956
T20	556660	1	0	1
T48	829653	1	0	1
T49	0	1	0	0
T50	46875	0	0	1
T51	18198	0	0	1
T52	1314	0	0	1
T53	631381	0	0	1
T54	77939	0	0	1
T55	53465	0	0	1
T56	26604	0	0	1
T57	18792	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492621	455407829	0	0
T1	120502	120449	0	0
T2	399218	399123	0	0
T3	587883	587828	0	0
T4	225871	225863	0	0
T5	88550	88475	0	0
T6	944889	944827	0	0
T7	579461	579393	0	0
T8	136433	136345	0	0
T9	3552	2699	0	0
T10	789	733	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492621	2223547	0	0
T1	120502	832	0	0
T2	399218	832	0	0
T3	587883	2624	0	0
T4	225871	14372	0	0
T5	88550	832	0	0
T6	944889	4290	0	0
T7	579461	906	0	0
T8	136433	832	0	0
T9	3552	0	0	0
T10	789	0	0	0
T11	0	832	0	0
T24	0	676	0	0