Assert Coverage for Module : 
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
3347 | 
0 | 
0 | 
| T60 | 
11988 | 
7 | 
0 | 
0 | 
| T61 | 
3167 | 
144 | 
0 | 
0 | 
| T62 | 
54493 | 
5 | 
0 | 
0 | 
| T80 | 
13621 | 
243 | 
0 | 
0 | 
| T81 | 
20247 | 
2 | 
0 | 
0 | 
| T82 | 
18134 | 
2 | 
0 | 
0 | 
| T94 | 
4655 | 
14 | 
0 | 
0 | 
| T96 | 
27836 | 
5 | 
0 | 
0 | 
| T98 | 
14349 | 
7 | 
0 | 
0 | 
| T99 | 
2674 | 
4 | 
0 | 
0 | 
addr_swap_data_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
1168 | 
0 | 
0 | 
| T69 | 
3279 | 
12 | 
0 | 
0 | 
| T98 | 
14349 | 
6 | 
0 | 
0 | 
| T106 | 
74321 | 
523 | 
0 | 
0 | 
| T125 | 
7050 | 
9 | 
0 | 
0 | 
| T127 | 
12682 | 
3 | 
0 | 
0 | 
| T135 | 
18472 | 
37 | 
0 | 
0 | 
| T136 | 
22639 | 
69 | 
0 | 
0 | 
| T137 | 
4694 | 
4 | 
0 | 
0 | 
| T138 | 
7378 | 
9 | 
0 | 
0 | 
| T139 | 
13188 | 
36 | 
0 | 
0 | 
addr_swap_mask_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
1390 | 
0 | 
0 | 
| T98 | 
14349 | 
8 | 
0 | 
0 | 
| T106 | 
74321 | 
564 | 
0 | 
0 | 
| T125 | 
7050 | 
14 | 
0 | 
0 | 
| T127 | 
12682 | 
20 | 
0 | 
0 | 
| T135 | 
18472 | 
20 | 
0 | 
0 | 
| T136 | 
22639 | 
108 | 
0 | 
0 | 
| T137 | 
4694 | 
9 | 
0 | 
0 | 
| T138 | 
7378 | 
34 | 
0 | 
0 | 
| T139 | 
13188 | 
40 | 
0 | 
0 | 
| T140 | 
5860 | 
1 | 
0 | 
0 | 
cfg_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
1736 | 
0 | 
0 | 
| T98 | 
14349 | 
23 | 
0 | 
0 | 
| T106 | 
74321 | 
497 | 
0 | 
0 | 
| T125 | 
7050 | 
24 | 
0 | 
0 | 
| T127 | 
12682 | 
32 | 
0 | 
0 | 
| T135 | 
18472 | 
26 | 
0 | 
0 | 
| T136 | 
22639 | 
68 | 
0 | 
0 | 
| T137 | 
4694 | 
2 | 
0 | 
0 | 
| T138 | 
7378 | 
35 | 
0 | 
0 | 
| T139 | 
13188 | 
24 | 
0 | 
0 | 
| T140 | 
5860 | 
18 | 
0 | 
0 | 
cmd_filter_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
8352 | 
0 | 
0 | 
| T98 | 
14349 | 
80 | 
0 | 
0 | 
| T106 | 
74321 | 
506 | 
0 | 
0 | 
| T125 | 
7050 | 
27 | 
0 | 
0 | 
| T127 | 
12682 | 
369 | 
0 | 
0 | 
| T135 | 
18472 | 
38 | 
0 | 
0 | 
| T136 | 
22639 | 
92 | 
0 | 
0 | 
| T137 | 
4694 | 
147 | 
0 | 
0 | 
| T138 | 
7378 | 
42 | 
0 | 
0 | 
| T139 | 
13188 | 
27 | 
0 | 
0 | 
| T140 | 
5860 | 
94 | 
0 | 
0 | 
cmd_filter_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
7921 | 
0 | 
0 | 
| T98 | 
14349 | 
212 | 
0 | 
0 | 
| T106 | 
74321 | 
485 | 
0 | 
0 | 
| T125 | 
7050 | 
44 | 
0 | 
0 | 
| T127 | 
12682 | 
270 | 
0 | 
0 | 
| T135 | 
18472 | 
54 | 
0 | 
0 | 
| T136 | 
22639 | 
16 | 
0 | 
0 | 
| T137 | 
4694 | 
1 | 
0 | 
0 | 
| T138 | 
7378 | 
21 | 
0 | 
0 | 
| T139 | 
13188 | 
35 | 
0 | 
0 | 
| T140 | 
5860 | 
39 | 
0 | 
0 | 
cmd_filter_2_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
8727 | 
0 | 
0 | 
| T98 | 
14349 | 
63 | 
0 | 
0 | 
| T106 | 
74321 | 
488 | 
0 | 
0 | 
| T125 | 
7050 | 
23 | 
0 | 
0 | 
| T127 | 
12682 | 
226 | 
0 | 
0 | 
| T135 | 
18472 | 
33 | 
0 | 
0 | 
| T136 | 
22639 | 
65 | 
0 | 
0 | 
| T137 | 
4694 | 
120 | 
0 | 
0 | 
| T138 | 
7378 | 
21 | 
0 | 
0 | 
| T139 | 
13188 | 
54 | 
0 | 
0 | 
| T140 | 
5860 | 
7 | 
0 | 
0 | 
cmd_filter_3_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
8432 | 
0 | 
0 | 
| T69 | 
3279 | 
7 | 
0 | 
0 | 
| T98 | 
14349 | 
185 | 
0 | 
0 | 
| T106 | 
74321 | 
536 | 
0 | 
0 | 
| T125 | 
7050 | 
29 | 
0 | 
0 | 
| T127 | 
12682 | 
22 | 
0 | 
0 | 
| T135 | 
18472 | 
25 | 
0 | 
0 | 
| T136 | 
22639 | 
36 | 
0 | 
0 | 
| T138 | 
7378 | 
20 | 
0 | 
0 | 
| T139 | 
13188 | 
27 | 
0 | 
0 | 
| T140 | 
5860 | 
9 | 
0 | 
0 | 
cmd_filter_4_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
8588 | 
0 | 
0 | 
| T69 | 
3279 | 
10 | 
0 | 
0 | 
| T98 | 
14349 | 
183 | 
0 | 
0 | 
| T106 | 
74321 | 
507 | 
0 | 
0 | 
| T127 | 
12682 | 
132 | 
0 | 
0 | 
| T135 | 
18472 | 
49 | 
0 | 
0 | 
| T136 | 
22639 | 
51 | 
0 | 
0 | 
| T138 | 
7378 | 
27 | 
0 | 
0 | 
| T139 | 
13188 | 
52 | 
0 | 
0 | 
| T140 | 
5860 | 
98 | 
0 | 
0 | 
| T141 | 
14595 | 
257 | 
0 | 
0 | 
cmd_filter_5_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
9203 | 
0 | 
0 | 
| T98 | 
14349 | 
67 | 
0 | 
0 | 
| T106 | 
74321 | 
492 | 
0 | 
0 | 
| T125 | 
7050 | 
7 | 
0 | 
0 | 
| T127 | 
12682 | 
253 | 
0 | 
0 | 
| T135 | 
18472 | 
14 | 
0 | 
0 | 
| T136 | 
22639 | 
71 | 
0 | 
0 | 
| T137 | 
4694 | 
135 | 
0 | 
0 | 
| T138 | 
7378 | 
19 | 
0 | 
0 | 
| T139 | 
13188 | 
63 | 
0 | 
0 | 
| T140 | 
5860 | 
3 | 
0 | 
0 | 
cmd_filter_6_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
7492 | 
0 | 
0 | 
| T98 | 
14349 | 
55 | 
0 | 
0 | 
| T106 | 
74321 | 
482 | 
0 | 
0 | 
| T125 | 
7050 | 
20 | 
0 | 
0 | 
| T127 | 
12682 | 
248 | 
0 | 
0 | 
| T135 | 
18472 | 
39 | 
0 | 
0 | 
| T136 | 
22639 | 
103 | 
0 | 
0 | 
| T137 | 
4694 | 
8 | 
0 | 
0 | 
| T138 | 
7378 | 
27 | 
0 | 
0 | 
| T139 | 
13188 | 
17 | 
0 | 
0 | 
| T140 | 
5860 | 
61 | 
0 | 
0 | 
cmd_filter_7_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
6697 | 
0 | 
0 | 
| T98 | 
14349 | 
75 | 
0 | 
0 | 
| T106 | 
74321 | 
529 | 
0 | 
0 | 
| T125 | 
7050 | 
42 | 
0 | 
0 | 
| T127 | 
12682 | 
249 | 
0 | 
0 | 
| T135 | 
18472 | 
68 | 
0 | 
0 | 
| T136 | 
22639 | 
72 | 
0 | 
0 | 
| T137 | 
4694 | 
2 | 
0 | 
0 | 
| T138 | 
7378 | 
4 | 
0 | 
0 | 
| T139 | 
13188 | 
23 | 
0 | 
0 | 
| T140 | 
5860 | 
103 | 
0 | 
0 | 
cmd_info_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
4194 | 
0 | 
0 | 
| T98 | 
14349 | 
45 | 
0 | 
0 | 
| T106 | 
74321 | 
507 | 
0 | 
0 | 
| T125 | 
7050 | 
13 | 
0 | 
0 | 
| T127 | 
12682 | 
16 | 
0 | 
0 | 
| T135 | 
18472 | 
52 | 
0 | 
0 | 
| T136 | 
22639 | 
98 | 
0 | 
0 | 
| T137 | 
4694 | 
9 | 
0 | 
0 | 
| T138 | 
7378 | 
10 | 
0 | 
0 | 
| T139 | 
13188 | 
17 | 
0 | 
0 | 
| T140 | 
5860 | 
32 | 
0 | 
0 | 
cmd_info_10_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
4120 | 
0 | 
0 | 
| T98 | 
14349 | 
48 | 
0 | 
0 | 
| T106 | 
74321 | 
504 | 
0 | 
0 | 
| T125 | 
7050 | 
19 | 
0 | 
0 | 
| T127 | 
12682 | 
52 | 
0 | 
0 | 
| T135 | 
18472 | 
23 | 
0 | 
0 | 
| T136 | 
22639 | 
28 | 
0 | 
0 | 
| T137 | 
4694 | 
2 | 
0 | 
0 | 
| T138 | 
7378 | 
30 | 
0 | 
0 | 
| T139 | 
13188 | 
58 | 
0 | 
0 | 
| T140 | 
5860 | 
38 | 
0 | 
0 | 
cmd_info_11_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
4389 | 
0 | 
0 | 
| T69 | 
3279 | 
8 | 
0 | 
0 | 
| T98 | 
14349 | 
132 | 
0 | 
0 | 
| T106 | 
74321 | 
511 | 
0 | 
0 | 
| T125 | 
7050 | 
26 | 
0 | 
0 | 
| T127 | 
12682 | 
126 | 
0 | 
0 | 
| T135 | 
18472 | 
53 | 
0 | 
0 | 
| T136 | 
22639 | 
64 | 
0 | 
0 | 
| T137 | 
4694 | 
51 | 
0 | 
0 | 
| T139 | 
13188 | 
36 | 
0 | 
0 | 
| T140 | 
5860 | 
32 | 
0 | 
0 | 
cmd_info_12_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
3961 | 
0 | 
0 | 
| T98 | 
14349 | 
70 | 
0 | 
0 | 
| T106 | 
74321 | 
475 | 
0 | 
0 | 
| T125 | 
7050 | 
4 | 
0 | 
0 | 
| T127 | 
12682 | 
72 | 
0 | 
0 | 
| T135 | 
18472 | 
59 | 
0 | 
0 | 
| T136 | 
22639 | 
105 | 
0 | 
0 | 
| T137 | 
4694 | 
39 | 
0 | 
0 | 
| T138 | 
7378 | 
19 | 
0 | 
0 | 
| T139 | 
13188 | 
21 | 
0 | 
0 | 
| T140 | 
5860 | 
37 | 
0 | 
0 | 
cmd_info_13_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
3940 | 
0 | 
0 | 
| T98 | 
14349 | 
3 | 
0 | 
0 | 
| T106 | 
74321 | 
475 | 
0 | 
0 | 
| T125 | 
7050 | 
3 | 
0 | 
0 | 
| T127 | 
12682 | 
128 | 
0 | 
0 | 
| T135 | 
18472 | 
38 | 
0 | 
0 | 
| T136 | 
22639 | 
99 | 
0 | 
0 | 
| T137 | 
4694 | 
6 | 
0 | 
0 | 
| T138 | 
7378 | 
6 | 
0 | 
0 | 
| T139 | 
13188 | 
70 | 
0 | 
0 | 
| T140 | 
5860 | 
2 | 
0 | 
0 | 
cmd_info_14_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
4103 | 
0 | 
0 | 
| T69 | 
3279 | 
10 | 
0 | 
0 | 
| T98 | 
14349 | 
58 | 
0 | 
0 | 
| T106 | 
74321 | 
501 | 
0 | 
0 | 
| T125 | 
7050 | 
21 | 
0 | 
0 | 
| T127 | 
12682 | 
68 | 
0 | 
0 | 
| T135 | 
18472 | 
22 | 
0 | 
0 | 
| T136 | 
22639 | 
50 | 
0 | 
0 | 
| T137 | 
4694 | 
50 | 
0 | 
0 | 
| T138 | 
7378 | 
4 | 
0 | 
0 | 
| T139 | 
13188 | 
15 | 
0 | 
0 | 
cmd_info_15_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
4548 | 
0 | 
0 | 
| T98 | 
14349 | 
60 | 
0 | 
0 | 
| T106 | 
74321 | 
470 | 
0 | 
0 | 
| T125 | 
7050 | 
27 | 
0 | 
0 | 
| T127 | 
12682 | 
136 | 
0 | 
0 | 
| T135 | 
18472 | 
26 | 
0 | 
0 | 
| T136 | 
22639 | 
79 | 
0 | 
0 | 
| T137 | 
4694 | 
3 | 
0 | 
0 | 
| T138 | 
7378 | 
23 | 
0 | 
0 | 
| T139 | 
13188 | 
22 | 
0 | 
0 | 
| T140 | 
5860 | 
21 | 
0 | 
0 | 
cmd_info_16_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
4055 | 
0 | 
0 | 
| T98 | 
14349 | 
41 | 
0 | 
0 | 
| T106 | 
74321 | 
521 | 
0 | 
0 | 
| T125 | 
7050 | 
8 | 
0 | 
0 | 
| T127 | 
12682 | 
174 | 
0 | 
0 | 
| T135 | 
18472 | 
10 | 
0 | 
0 | 
| T136 | 
22639 | 
128 | 
0 | 
0 | 
| T137 | 
4694 | 
56 | 
0 | 
0 | 
| T138 | 
7378 | 
36 | 
0 | 
0 | 
| T139 | 
13188 | 
47 | 
0 | 
0 | 
| T140 | 
5860 | 
36 | 
0 | 
0 | 
cmd_info_17_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
3802 | 
0 | 
0 | 
| T98 | 
14349 | 
60 | 
0 | 
0 | 
| T106 | 
74321 | 
510 | 
0 | 
0 | 
| T125 | 
7050 | 
24 | 
0 | 
0 | 
| T127 | 
12682 | 
71 | 
0 | 
0 | 
| T135 | 
18472 | 
15 | 
0 | 
0 | 
| T136 | 
22639 | 
90 | 
0 | 
0 | 
| T137 | 
4694 | 
46 | 
0 | 
0 | 
| T138 | 
7378 | 
26 | 
0 | 
0 | 
| T139 | 
13188 | 
37 | 
0 | 
0 | 
| T140 | 
5860 | 
2 | 
0 | 
0 | 
cmd_info_18_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
4014 | 
0 | 
0 | 
| T98 | 
14349 | 
83 | 
0 | 
0 | 
| T106 | 
74321 | 
487 | 
0 | 
0 | 
| T125 | 
7050 | 
14 | 
0 | 
0 | 
| T127 | 
12682 | 
157 | 
0 | 
0 | 
| T135 | 
18472 | 
53 | 
0 | 
0 | 
| T136 | 
22639 | 
69 | 
0 | 
0 | 
| T137 | 
4694 | 
54 | 
0 | 
0 | 
| T138 | 
7378 | 
24 | 
0 | 
0 | 
| T139 | 
13188 | 
58 | 
0 | 
0 | 
| T140 | 
5860 | 
7 | 
0 | 
0 | 
cmd_info_19_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
4001 | 
0 | 
0 | 
| T98 | 
14349 | 
24 | 
0 | 
0 | 
| T106 | 
74321 | 
520 | 
0 | 
0 | 
| T125 | 
7050 | 
17 | 
0 | 
0 | 
| T127 | 
12682 | 
95 | 
0 | 
0 | 
| T135 | 
18472 | 
45 | 
0 | 
0 | 
| T136 | 
22639 | 
92 | 
0 | 
0 | 
| T137 | 
4694 | 
70 | 
0 | 
0 | 
| T138 | 
7378 | 
40 | 
0 | 
0 | 
| T139 | 
13188 | 
36 | 
0 | 
0 | 
| T140 | 
5860 | 
8 | 
0 | 
0 | 
cmd_info_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
4407 | 
0 | 
0 | 
| T98 | 
14349 | 
52 | 
0 | 
0 | 
| T106 | 
74321 | 
487 | 
0 | 
0 | 
| T125 | 
7050 | 
30 | 
0 | 
0 | 
| T127 | 
12682 | 
165 | 
0 | 
0 | 
| T135 | 
18472 | 
38 | 
0 | 
0 | 
| T136 | 
22639 | 
102 | 
0 | 
0 | 
| T137 | 
4694 | 
46 | 
0 | 
0 | 
| T138 | 
7378 | 
26 | 
0 | 
0 | 
| T139 | 
13188 | 
72 | 
0 | 
0 | 
| T140 | 
5860 | 
22 | 
0 | 
0 | 
cmd_info_20_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
4424 | 
0 | 
0 | 
| T69 | 
3279 | 
4 | 
0 | 
0 | 
| T98 | 
14349 | 
68 | 
0 | 
0 | 
| T106 | 
74321 | 
523 | 
0 | 
0 | 
| T125 | 
7050 | 
37 | 
0 | 
0 | 
| T127 | 
12682 | 
127 | 
0 | 
0 | 
| T135 | 
18472 | 
57 | 
0 | 
0 | 
| T136 | 
22639 | 
42 | 
0 | 
0 | 
| T137 | 
4694 | 
64 | 
0 | 
0 | 
| T138 | 
7378 | 
16 | 
0 | 
0 | 
| T139 | 
13188 | 
61 | 
0 | 
0 | 
cmd_info_21_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
3821 | 
0 | 
0 | 
| T69 | 
3279 | 
3 | 
0 | 
0 | 
| T98 | 
14349 | 
39 | 
0 | 
0 | 
| T106 | 
74321 | 
481 | 
0 | 
0 | 
| T125 | 
7050 | 
22 | 
0 | 
0 | 
| T127 | 
12682 | 
48 | 
0 | 
0 | 
| T135 | 
18472 | 
20 | 
0 | 
0 | 
| T136 | 
22639 | 
33 | 
0 | 
0 | 
| T137 | 
4694 | 
50 | 
0 | 
0 | 
| T138 | 
7378 | 
31 | 
0 | 
0 | 
| T139 | 
13188 | 
48 | 
0 | 
0 | 
cmd_info_22_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
4233 | 
0 | 
0 | 
| T98 | 
14349 | 
82 | 
0 | 
0 | 
| T106 | 
74321 | 
570 | 
0 | 
0 | 
| T125 | 
7050 | 
12 | 
0 | 
0 | 
| T127 | 
12682 | 
46 | 
0 | 
0 | 
| T135 | 
18472 | 
8 | 
0 | 
0 | 
| T136 | 
22639 | 
20 | 
0 | 
0 | 
| T137 | 
4694 | 
66 | 
0 | 
0 | 
| T138 | 
7378 | 
13 | 
0 | 
0 | 
| T139 | 
13188 | 
84 | 
0 | 
0 | 
| T140 | 
5860 | 
44 | 
0 | 
0 | 
cmd_info_23_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
4392 | 
0 | 
0 | 
| T98 | 
14349 | 
26 | 
0 | 
0 | 
| T106 | 
74321 | 
492 | 
0 | 
0 | 
| T125 | 
7050 | 
22 | 
0 | 
0 | 
| T127 | 
12682 | 
102 | 
0 | 
0 | 
| T135 | 
18472 | 
73 | 
0 | 
0 | 
| T136 | 
22639 | 
67 | 
0 | 
0 | 
| T137 | 
4694 | 
50 | 
0 | 
0 | 
| T138 | 
7378 | 
23 | 
0 | 
0 | 
| T139 | 
13188 | 
56 | 
0 | 
0 | 
| T140 | 
5860 | 
45 | 
0 | 
0 | 
cmd_info_2_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
3556 | 
0 | 
0 | 
| T98 | 
14349 | 
70 | 
0 | 
0 | 
| T106 | 
74321 | 
462 | 
0 | 
0 | 
| T125 | 
7050 | 
45 | 
0 | 
0 | 
| T127 | 
12682 | 
15 | 
0 | 
0 | 
| T135 | 
18472 | 
39 | 
0 | 
0 | 
| T136 | 
22639 | 
67 | 
0 | 
0 | 
| T137 | 
4694 | 
47 | 
0 | 
0 | 
| T138 | 
7378 | 
4 | 
0 | 
0 | 
| T139 | 
13188 | 
27 | 
0 | 
0 | 
| T140 | 
5860 | 
9 | 
0 | 
0 | 
cmd_info_3_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
3590 | 
0 | 
0 | 
| T98 | 
14349 | 
62 | 
0 | 
0 | 
| T106 | 
74321 | 
423 | 
0 | 
0 | 
| T125 | 
7050 | 
5 | 
0 | 
0 | 
| T127 | 
12682 | 
60 | 
0 | 
0 | 
| T135 | 
18472 | 
33 | 
0 | 
0 | 
| T136 | 
22639 | 
33 | 
0 | 
0 | 
| T137 | 
4694 | 
48 | 
0 | 
0 | 
| T138 | 
7378 | 
27 | 
0 | 
0 | 
| T139 | 
13188 | 
28 | 
0 | 
0 | 
| T140 | 
5860 | 
12 | 
0 | 
0 | 
cmd_info_4_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
4088 | 
0 | 
0 | 
| T98 | 
14349 | 
78 | 
0 | 
0 | 
| T106 | 
74321 | 
494 | 
0 | 
0 | 
| T125 | 
7050 | 
15 | 
0 | 
0 | 
| T127 | 
12682 | 
58 | 
0 | 
0 | 
| T135 | 
18472 | 
35 | 
0 | 
0 | 
| T136 | 
22639 | 
60 | 
0 | 
0 | 
| T137 | 
4694 | 
9 | 
0 | 
0 | 
| T138 | 
7378 | 
8 | 
0 | 
0 | 
| T139 | 
13188 | 
42 | 
0 | 
0 | 
| T140 | 
5860 | 
22 | 
0 | 
0 | 
cmd_info_5_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
3734 | 
0 | 
0 | 
| T98 | 
14349 | 
42 | 
0 | 
0 | 
| T106 | 
74321 | 
495 | 
0 | 
0 | 
| T125 | 
7050 | 
33 | 
0 | 
0 | 
| T127 | 
12682 | 
123 | 
0 | 
0 | 
| T135 | 
18472 | 
12 | 
0 | 
0 | 
| T136 | 
22639 | 
73 | 
0 | 
0 | 
| T137 | 
4694 | 
7 | 
0 | 
0 | 
| T138 | 
7378 | 
17 | 
0 | 
0 | 
| T139 | 
13188 | 
32 | 
0 | 
0 | 
| T140 | 
5860 | 
50 | 
0 | 
0 | 
cmd_info_6_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
3999 | 
0 | 
0 | 
| T98 | 
14349 | 
18 | 
0 | 
0 | 
| T106 | 
74321 | 
492 | 
0 | 
0 | 
| T125 | 
7050 | 
1 | 
0 | 
0 | 
| T127 | 
12682 | 
53 | 
0 | 
0 | 
| T135 | 
18472 | 
34 | 
0 | 
0 | 
| T136 | 
22639 | 
35 | 
0 | 
0 | 
| T137 | 
4694 | 
53 | 
0 | 
0 | 
| T138 | 
7378 | 
27 | 
0 | 
0 | 
| T139 | 
13188 | 
59 | 
0 | 
0 | 
| T140 | 
5860 | 
8 | 
0 | 
0 | 
cmd_info_7_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
3607 | 
0 | 
0 | 
| T69 | 
3279 | 
9 | 
0 | 
0 | 
| T98 | 
14349 | 
31 | 
0 | 
0 | 
| T106 | 
74321 | 
507 | 
0 | 
0 | 
| T125 | 
7050 | 
11 | 
0 | 
0 | 
| T127 | 
12682 | 
94 | 
0 | 
0 | 
| T135 | 
18472 | 
26 | 
0 | 
0 | 
| T136 | 
22639 | 
94 | 
0 | 
0 | 
| T137 | 
4694 | 
8 | 
0 | 
0 | 
| T138 | 
7378 | 
5 | 
0 | 
0 | 
| T139 | 
13188 | 
79 | 
0 | 
0 | 
cmd_info_8_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
3786 | 
0 | 
0 | 
| T69 | 
3279 | 
10 | 
0 | 
0 | 
| T98 | 
14349 | 
34 | 
0 | 
0 | 
| T106 | 
74321 | 
509 | 
0 | 
0 | 
| T125 | 
7050 | 
5 | 
0 | 
0 | 
| T127 | 
12682 | 
116 | 
0 | 
0 | 
| T135 | 
18472 | 
29 | 
0 | 
0 | 
| T136 | 
22639 | 
79 | 
0 | 
0 | 
| T137 | 
4694 | 
1 | 
0 | 
0 | 
| T138 | 
7378 | 
16 | 
0 | 
0 | 
| T139 | 
13188 | 
33 | 
0 | 
0 | 
cmd_info_9_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
3879 | 
0 | 
0 | 
| T69 | 
3279 | 
3 | 
0 | 
0 | 
| T98 | 
14349 | 
41 | 
0 | 
0 | 
| T106 | 
74321 | 
439 | 
0 | 
0 | 
| T125 | 
7050 | 
12 | 
0 | 
0 | 
| T127 | 
12682 | 
80 | 
0 | 
0 | 
| T135 | 
18472 | 
56 | 
0 | 
0 | 
| T136 | 
22639 | 
54 | 
0 | 
0 | 
| T138 | 
7378 | 
5 | 
0 | 
0 | 
| T139 | 
13188 | 
36 | 
0 | 
0 | 
| T140 | 
5860 | 
3 | 
0 | 
0 | 
cmd_info_en4b_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
1484 | 
0 | 
0 | 
| T69 | 
3279 | 
6 | 
0 | 
0 | 
| T98 | 
14349 | 
12 | 
0 | 
0 | 
| T106 | 
74321 | 
500 | 
0 | 
0 | 
| T125 | 
7050 | 
33 | 
0 | 
0 | 
| T127 | 
12682 | 
35 | 
0 | 
0 | 
| T135 | 
18472 | 
31 | 
0 | 
0 | 
| T136 | 
22639 | 
40 | 
0 | 
0 | 
| T137 | 
4694 | 
5 | 
0 | 
0 | 
| T139 | 
13188 | 
65 | 
0 | 
0 | 
| T140 | 
5860 | 
4 | 
0 | 
0 | 
cmd_info_ex4b_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
1445 | 
0 | 
0 | 
| T69 | 
3279 | 
3 | 
0 | 
0 | 
| T98 | 
14349 | 
36 | 
0 | 
0 | 
| T106 | 
74321 | 
494 | 
0 | 
0 | 
| T125 | 
7050 | 
38 | 
0 | 
0 | 
| T127 | 
12682 | 
15 | 
0 | 
0 | 
| T135 | 
18472 | 
12 | 
0 | 
0 | 
| T136 | 
22639 | 
56 | 
0 | 
0 | 
| T137 | 
4694 | 
1 | 
0 | 
0 | 
| T139 | 
13188 | 
14 | 
0 | 
0 | 
| T140 | 
5860 | 
9 | 
0 | 
0 | 
cmd_info_wrdi_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
1496 | 
0 | 
0 | 
| T98 | 
14349 | 
5 | 
0 | 
0 | 
| T106 | 
74321 | 
486 | 
0 | 
0 | 
| T125 | 
7050 | 
42 | 
0 | 
0 | 
| T127 | 
12682 | 
14 | 
0 | 
0 | 
| T135 | 
18472 | 
40 | 
0 | 
0 | 
| T136 | 
22639 | 
65 | 
0 | 
0 | 
| T137 | 
4694 | 
6 | 
0 | 
0 | 
| T138 | 
7378 | 
40 | 
0 | 
0 | 
| T139 | 
13188 | 
41 | 
0 | 
0 | 
| T140 | 
5860 | 
1 | 
0 | 
0 | 
cmd_info_wren_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
1360 | 
0 | 
0 | 
| T98 | 
14349 | 
15 | 
0 | 
0 | 
| T106 | 
74321 | 
494 | 
0 | 
0 | 
| T125 | 
7050 | 
34 | 
0 | 
0 | 
| T127 | 
12682 | 
8 | 
0 | 
0 | 
| T135 | 
18472 | 
37 | 
0 | 
0 | 
| T136 | 
22639 | 
60 | 
0 | 
0 | 
| T137 | 
4694 | 
13 | 
0 | 
0 | 
| T138 | 
7378 | 
34 | 
0 | 
0 | 
| T139 | 
13188 | 
8 | 
0 | 
0 | 
| T140 | 
5860 | 
3 | 
0 | 
0 | 
intercept_en_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
1873 | 
0 | 
0 | 
| T98 | 
14349 | 
43 | 
0 | 
0 | 
| T106 | 
74321 | 
473 | 
0 | 
0 | 
| T125 | 
7050 | 
22 | 
0 | 
0 | 
| T127 | 
12682 | 
28 | 
0 | 
0 | 
| T135 | 
18472 | 
23 | 
0 | 
0 | 
| T136 | 
22639 | 
46 | 
0 | 
0 | 
| T137 | 
4694 | 
14 | 
0 | 
0 | 
| T138 | 
7378 | 
9 | 
0 | 
0 | 
| T139 | 
13188 | 
35 | 
0 | 
0 | 
| T140 | 
5860 | 
6 | 
0 | 
0 | 
intr_enable_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
3763 | 
0 | 
0 | 
| T16 | 
448645 | 
20 | 
0 | 
0 | 
| T17 | 
244681 | 
0 | 
0 | 
0 | 
| T18 | 
752801 | 
0 | 
0 | 
0 | 
| T19 | 
0 | 
34 | 
0 | 
0 | 
| T22 | 
0 | 
18 | 
0 | 
0 | 
| T41 | 
365662 | 
0 | 
0 | 
0 | 
| T42 | 
213355 | 
0 | 
0 | 
0 | 
| T129 | 
21761 | 
0 | 
0 | 
0 | 
| T142 | 
0 | 
17 | 
0 | 
0 | 
| T143 | 
0 | 
52 | 
0 | 
0 | 
| T144 | 
0 | 
24 | 
0 | 
0 | 
| T145 | 
0 | 
12 | 
0 | 
0 | 
| T146 | 
0 | 
54 | 
0 | 
0 | 
| T147 | 
0 | 
76 | 
0 | 
0 | 
| T148 | 
0 | 
74 | 
0 | 
0 | 
| T149 | 
187919 | 
0 | 
0 | 
0 | 
| T150 | 
2749 | 
0 | 
0 | 
0 | 
| T151 | 
7395 | 
0 | 
0 | 
0 | 
| T152 | 
1049 | 
0 | 
0 | 
0 | 
jedec_cc_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
1586 | 
0 | 
0 | 
| T69 | 
3279 | 
5 | 
0 | 
0 | 
| T98 | 
14349 | 
22 | 
0 | 
0 | 
| T106 | 
74321 | 
541 | 
0 | 
0 | 
| T127 | 
12682 | 
14 | 
0 | 
0 | 
| T135 | 
18472 | 
17 | 
0 | 
0 | 
| T136 | 
22639 | 
111 | 
0 | 
0 | 
| T138 | 
7378 | 
48 | 
0 | 
0 | 
| T139 | 
13188 | 
55 | 
0 | 
0 | 
| T140 | 
5860 | 
8 | 
0 | 
0 | 
| T141 | 
14595 | 
24 | 
0 | 
0 | 
jedec_id_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
1458 | 
0 | 
0 | 
| T98 | 
14349 | 
9 | 
0 | 
0 | 
| T106 | 
74321 | 
507 | 
0 | 
0 | 
| T125 | 
7050 | 
6 | 
0 | 
0 | 
| T127 | 
12682 | 
26 | 
0 | 
0 | 
| T135 | 
18472 | 
44 | 
0 | 
0 | 
| T136 | 
22639 | 
67 | 
0 | 
0 | 
| T137 | 
4694 | 
8 | 
0 | 
0 | 
| T138 | 
7378 | 
22 | 
0 | 
0 | 
| T139 | 
13188 | 
32 | 
0 | 
0 | 
| T140 | 
5860 | 
7 | 
0 | 
0 | 
mailbox_addr_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
1393 | 
0 | 
0 | 
| T98 | 
14349 | 
5 | 
0 | 
0 | 
| T106 | 
74321 | 
502 | 
0 | 
0 | 
| T125 | 
7050 | 
26 | 
0 | 
0 | 
| T127 | 
12682 | 
17 | 
0 | 
0 | 
| T135 | 
18472 | 
66 | 
0 | 
0 | 
| T136 | 
22639 | 
73 | 
0 | 
0 | 
| T137 | 
4694 | 
4 | 
0 | 
0 | 
| T138 | 
7378 | 
34 | 
0 | 
0 | 
| T139 | 
13188 | 
77 | 
0 | 
0 | 
| T140 | 
5860 | 
4 | 
0 | 
0 | 
payload_swap_data_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
1362 | 
0 | 
0 | 
| T69 | 
3279 | 
3 | 
0 | 
0 | 
| T98 | 
14349 | 
20 | 
0 | 
0 | 
| T106 | 
74321 | 
582 | 
0 | 
0 | 
| T125 | 
7050 | 
27 | 
0 | 
0 | 
| T127 | 
12682 | 
20 | 
0 | 
0 | 
| T135 | 
18472 | 
34 | 
0 | 
0 | 
| T136 | 
22639 | 
45 | 
0 | 
0 | 
| T137 | 
4694 | 
1 | 
0 | 
0 | 
| T139 | 
13188 | 
76 | 
0 | 
0 | 
| T140 | 
5860 | 
3 | 
0 | 
0 | 
payload_swap_mask_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
1276 | 
0 | 
0 | 
| T69 | 
3279 | 
6 | 
0 | 
0 | 
| T98 | 
14349 | 
6 | 
0 | 
0 | 
| T106 | 
74321 | 
456 | 
0 | 
0 | 
| T125 | 
7050 | 
35 | 
0 | 
0 | 
| T127 | 
12682 | 
15 | 
0 | 
0 | 
| T135 | 
18472 | 
22 | 
0 | 
0 | 
| T136 | 
22639 | 
49 | 
0 | 
0 | 
| T137 | 
4694 | 
6 | 
0 | 
0 | 
| T138 | 
7378 | 
47 | 
0 | 
0 | 
| T139 | 
13188 | 
38 | 
0 | 
0 | 
read_threshold_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
1250 | 
0 | 
0 | 
| T69 | 
3279 | 
1 | 
0 | 
0 | 
| T98 | 
14349 | 
21 | 
0 | 
0 | 
| T106 | 
74321 | 
500 | 
0 | 
0 | 
| T125 | 
7050 | 
15 | 
0 | 
0 | 
| T127 | 
12682 | 
13 | 
0 | 
0 | 
| T135 | 
18472 | 
15 | 
0 | 
0 | 
| T136 | 
22639 | 
71 | 
0 | 
0 | 
| T137 | 
4694 | 
7 | 
0 | 
0 | 
| T138 | 
7378 | 
31 | 
0 | 
0 | 
| T139 | 
13188 | 
27 | 
0 | 
0 | 
tpm_access_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
2002 | 
0 | 
0 | 
| T98 | 
14349 | 
45 | 
0 | 
0 | 
| T106 | 
74321 | 
496 | 
0 | 
0 | 
| T125 | 
7050 | 
14 | 
0 | 
0 | 
| T127 | 
12682 | 
54 | 
0 | 
0 | 
| T135 | 
18472 | 
20 | 
0 | 
0 | 
| T136 | 
22639 | 
61 | 
0 | 
0 | 
| T137 | 
4694 | 
3 | 
0 | 
0 | 
| T138 | 
7378 | 
32 | 
0 | 
0 | 
| T139 | 
13188 | 
27 | 
0 | 
0 | 
| T140 | 
5860 | 
3 | 
0 | 
0 | 
tpm_access_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
1281 | 
0 | 
0 | 
| T98 | 
14349 | 
10 | 
0 | 
0 | 
| T106 | 
74321 | 
499 | 
0 | 
0 | 
| T125 | 
7050 | 
24 | 
0 | 
0 | 
| T127 | 
12682 | 
2 | 
0 | 
0 | 
| T135 | 
18472 | 
43 | 
0 | 
0 | 
| T136 | 
22639 | 
77 | 
0 | 
0 | 
| T137 | 
4694 | 
5 | 
0 | 
0 | 
| T138 | 
7378 | 
10 | 
0 | 
0 | 
| T139 | 
13188 | 
31 | 
0 | 
0 | 
| T140 | 
5860 | 
9 | 
0 | 
0 | 
tpm_cfg_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
2215 | 
0 | 
0 | 
| T69 | 
3279 | 
7 | 
0 | 
0 | 
| T98 | 
14349 | 
11 | 
0 | 
0 | 
| T106 | 
74321 | 
525 | 
0 | 
0 | 
| T125 | 
7050 | 
16 | 
0 | 
0 | 
| T127 | 
12682 | 
26 | 
0 | 
0 | 
| T135 | 
18472 | 
53 | 
0 | 
0 | 
| T136 | 
22639 | 
54 | 
0 | 
0 | 
| T138 | 
7378 | 
13 | 
0 | 
0 | 
| T139 | 
13188 | 
92 | 
0 | 
0 | 
| T140 | 
5860 | 
2 | 
0 | 
0 | 
tpm_did_vid_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
1330 | 
0 | 
0 | 
| T69 | 
3279 | 
9 | 
0 | 
0 | 
| T98 | 
14349 | 
34 | 
0 | 
0 | 
| T106 | 
74321 | 
458 | 
0 | 
0 | 
| T125 | 
7050 | 
5 | 
0 | 
0 | 
| T127 | 
12682 | 
14 | 
0 | 
0 | 
| T135 | 
18472 | 
34 | 
0 | 
0 | 
| T136 | 
22639 | 
54 | 
0 | 
0 | 
| T137 | 
4694 | 
4 | 
0 | 
0 | 
| T138 | 
7378 | 
30 | 
0 | 
0 | 
| T139 | 
13188 | 
42 | 
0 | 
0 | 
tpm_int_enable_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
1148 | 
0 | 
0 | 
| T98 | 
14349 | 
17 | 
0 | 
0 | 
| T106 | 
74321 | 
454 | 
0 | 
0 | 
| T125 | 
7050 | 
14 | 
0 | 
0 | 
| T127 | 
12682 | 
15 | 
0 | 
0 | 
| T135 | 
18472 | 
44 | 
0 | 
0 | 
| T136 | 
22639 | 
53 | 
0 | 
0 | 
| T137 | 
4694 | 
1 | 
0 | 
0 | 
| T138 | 
7378 | 
25 | 
0 | 
0 | 
| T139 | 
13188 | 
35 | 
0 | 
0 | 
| T140 | 
5860 | 
5 | 
0 | 
0 | 
tpm_int_status_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
1328 | 
0 | 
0 | 
| T98 | 
14349 | 
14 | 
0 | 
0 | 
| T106 | 
74321 | 
514 | 
0 | 
0 | 
| T125 | 
7050 | 
5 | 
0 | 
0 | 
| T127 | 
12682 | 
10 | 
0 | 
0 | 
| T135 | 
18472 | 
36 | 
0 | 
0 | 
| T136 | 
22639 | 
98 | 
0 | 
0 | 
| T137 | 
4694 | 
5 | 
0 | 
0 | 
| T138 | 
7378 | 
6 | 
0 | 
0 | 
| T139 | 
13188 | 
92 | 
0 | 
0 | 
| T140 | 
5860 | 
7 | 
0 | 
0 | 
tpm_int_vector_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
1277 | 
0 | 
0 | 
| T98 | 
14349 | 
2 | 
0 | 
0 | 
| T106 | 
74321 | 
502 | 
0 | 
0 | 
| T125 | 
7050 | 
40 | 
0 | 
0 | 
| T127 | 
12682 | 
12 | 
0 | 
0 | 
| T135 | 
18472 | 
38 | 
0 | 
0 | 
| T136 | 
22639 | 
62 | 
0 | 
0 | 
| T137 | 
4694 | 
1 | 
0 | 
0 | 
| T138 | 
7378 | 
56 | 
0 | 
0 | 
| T139 | 
13188 | 
29 | 
0 | 
0 | 
| T140 | 
5860 | 
5 | 
0 | 
0 | 
tpm_intf_capability_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
1323 | 
0 | 
0 | 
| T98 | 
14349 | 
14 | 
0 | 
0 | 
| T106 | 
74321 | 
515 | 
0 | 
0 | 
| T125 | 
7050 | 
37 | 
0 | 
0 | 
| T127 | 
12682 | 
9 | 
0 | 
0 | 
| T135 | 
18472 | 
15 | 
0 | 
0 | 
| T136 | 
22639 | 
77 | 
0 | 
0 | 
| T137 | 
4694 | 
5 | 
0 | 
0 | 
| T138 | 
7378 | 
48 | 
0 | 
0 | 
| T139 | 
13188 | 
9 | 
0 | 
0 | 
| T140 | 
5860 | 
3 | 
0 | 
0 | 
tpm_rid_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
1193 | 
0 | 
0 | 
| T98 | 
14349 | 
6 | 
0 | 
0 | 
| T106 | 
74321 | 
485 | 
0 | 
0 | 
| T125 | 
7050 | 
41 | 
0 | 
0 | 
| T127 | 
12682 | 
10 | 
0 | 
0 | 
| T135 | 
18472 | 
16 | 
0 | 
0 | 
| T136 | 
22639 | 
77 | 
0 | 
0 | 
| T137 | 
4694 | 
6 | 
0 | 
0 | 
| T138 | 
7378 | 
7 | 
0 | 
0 | 
| T139 | 
13188 | 
36 | 
0 | 
0 | 
| T140 | 
5860 | 
9 | 
0 | 
0 | 
tpm_sts_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457926760 | 
1263 | 
0 | 
0 | 
| T98 | 
14349 | 
14 | 
0 | 
0 | 
| T106 | 
74321 | 
517 | 
0 | 
0 | 
| T125 | 
7050 | 
28 | 
0 | 
0 | 
| T127 | 
12682 | 
5 | 
0 | 
0 | 
| T135 | 
18472 | 
43 | 
0 | 
0 | 
| T136 | 
22639 | 
46 | 
0 | 
0 | 
| T137 | 
4694 | 
3 | 
0 | 
0 | 
| T138 | 
7378 | 
5 | 
0 | 
0 | 
| T139 | 
13188 | 
17 | 
0 | 
0 | 
| T140 | 
5860 | 
10 | 
0 | 
0 |