Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3083044	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4054264

1

T1

2264

T2

1172

T3

886

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3849039	1			T1	4375		T2	1831		T3	13
values[0x0]	1641691	1			T1	1106		T2	556		T3	480
values[0x1]	1646578	1			T1	1131		T2	593		T3	408

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2207554	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4929754

1

T1

3649

T2

1733

T3

888

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	25210	1			T1	22		T2	11		T3	5
valid_sources[0x01]	24497	1			T1	19		T2	6		T3	4
valid_sources[0x02]	28446	1			T1	27		T2	12		T3	4
valid_sources[0x03]	28909	1			T1	21		T2	25		T3	3
valid_sources[0x04]	28351	1			T1	23		T2	29		T5	43
valid_sources[0x05]	27637	1			T1	22		T2	14		T3	5
valid_sources[0x06]	29621	1			T1	26		T2	9		T3	2
valid_sources[0x07]	27553	1			T1	31		T2	13		T3	5
valid_sources[0x08]	26785	1			T1	20		T2	6		T3	2
valid_sources[0x09]	25535	1			T1	31		T2	9		T3	7
valid_sources[0x0a]	28383	1			T1	25		T2	15		T3	1
valid_sources[0x0b]	28390	1			T1	34		T2	10		T3	3
valid_sources[0x0c]	26409	1			T1	23		T2	19		T3	3
valid_sources[0x0d]	25387	1			T1	26		T2	4		T3	2
valid_sources[0x0e]	27664	1			T1	30		T2	19		T3	6
valid_sources[0x0f]	27776	1			T1	24		T2	15		T3	4
valid_sources[0x10]	27394	1			T1	27		T2	15		T3	1
valid_sources[0x11]	26360	1			T1	29		T2	18		T3	4
valid_sources[0x12]	28771	1			T1	24		T2	6		T3	4
valid_sources[0x13]	26957	1			T1	26		T2	13		T3	2
valid_sources[0x14]	26986	1			T1	20		T2	9		T3	4
valid_sources[0x15]	29183	1			T1	23		T2	9		T3	2
valid_sources[0x16]	25536	1			T1	30		T2	32		T3	7
valid_sources[0x17]	27110	1			T1	22		T2	2		T3	3
valid_sources[0x18]	26763	1			T1	19		T2	10		T3	6
valid_sources[0x19]	26715	1			T1	32		T2	12		T3	4
valid_sources[0x1a]	26314	1			T1	28		T2	3		T3	3
valid_sources[0x1b]	31857	1			T1	23		T2	9		T3	3
valid_sources[0x1c]	43882	1			T1	28		T2	2		T3	6
valid_sources[0x1d]	25698	1			T1	29		T2	18		T3	4
valid_sources[0x1e]	25374	1			T1	35		T2	6		T3	1
valid_sources[0x1f]	27586	1			T1	33		T2	8		T3	1
valid_sources[0x20]	24620	1			T1	16		T2	17		T3	5
valid_sources[0x21]	24647	1			T1	21		T2	18		T3	2
valid_sources[0x22]	26011	1			T1	17		T2	9		T3	2
valid_sources[0x23]	29616	1			T1	24		T2	9		T3	4
valid_sources[0x24]	28275	1			T1	25		T2	15		T3	2
valid_sources[0x25]	34495	1			T1	22		T2	8		T3	3
valid_sources[0x26]	25692	1			T1	20		T2	25		T3	2
valid_sources[0x27]	26924	1			T1	36		T2	7		T3	1
valid_sources[0x28]	24577	1			T1	23		T2	12		T3	4
valid_sources[0x29]	29731	1			T1	24		T2	5		T3	7
valid_sources[0x2a]	27580	1			T1	40		T2	7		T3	2
valid_sources[0x2b]	25635	1			T1	36		T2	3		T3	2
valid_sources[0x2c]	27221	1			T1	10		T2	13		T3	5
valid_sources[0x2d]	26864	1			T1	28		T2	10		T3	5
valid_sources[0x2e]	28777	1			T1	24		T2	26		T3	3
valid_sources[0x2f]	26096	1			T1	24		T2	8		T3	3
valid_sources[0x30]	32702	1			T1	31		T2	5		T3	4
valid_sources[0x31]	25795	1			T1	20		T2	13		T3	4
valid_sources[0x32]	29952	1			T1	31		T2	11		T3	4
valid_sources[0x33]	27452	1			T1	19		T2	20		T3	5
valid_sources[0x34]	24319	1			T1	21		T2	6		T3	2
valid_sources[0x35]	27573	1			T1	23		T2	17		T3	2
valid_sources[0x36]	26673	1			T1	25		T2	11		T3	5
valid_sources[0x37]	30689	1			T1	21		T2	2		T3	1
valid_sources[0x38]	25556	1			T1	28		T2	14		T3	4
valid_sources[0x39]	26376	1			T1	36		T2	7		T3	5
valid_sources[0x3a]	25858	1			T1	23		T2	9		T3	2
valid_sources[0x3b]	27639	1			T1	21		T2	5		T3	5
valid_sources[0x3c]	30541	1			T1	29		T2	12		T3	2
valid_sources[0x3d]	26586	1			T1	23		T2	8		T3	7
valid_sources[0x3e]	27459	1			T1	29		T2	20		T3	4
valid_sources[0x3f]	27632	1			T1	15		T2	11		T3	4
valid_sources[0x40]	26447	1			T1	29		T2	19		T3	1
valid_sources[0x41]	27358	1			T1	23		T2	22		T3	4
valid_sources[0x42]	32873	1			T1	27		T2	16		T3	3
valid_sources[0x43]	27510	1			T1	28		T2	15		T3	3
valid_sources[0x44]	25624	1			T1	24		T2	4		T3	5
valid_sources[0x45]	26797	1			T1	29		T2	14		T3	5
valid_sources[0x46]	26356	1			T1	36		T2	9		T3	2
valid_sources[0x47]	27093	1			T1	33		T2	6		T3	2
valid_sources[0x48]	26375	1			T1	26		T2	13		T5	49
valid_sources[0x49]	30122	1			T1	28		T2	16		T3	3
valid_sources[0x4a]	26539	1			T1	39		T2	6		T3	3
valid_sources[0x4b]	26702	1			T1	24		T2	9		T3	3
valid_sources[0x4c]	24940	1			T1	24		T2	4		T3	5
valid_sources[0x4d]	29063	1			T1	18		T2	10		T3	6
valid_sources[0x4e]	28074	1			T1	31		T2	12		T3	3
valid_sources[0x4f]	28869	1			T1	30		T2	29		T3	1
valid_sources[0x50]	31625	1			T1	30		T2	6		T3	3
valid_sources[0x51]	25475	1			T1	37		T2	4		T3	4
valid_sources[0x52]	26198	1			T1	24		T2	24		T3	5
valid_sources[0x53]	25986	1			T1	27		T2	16		T3	1
valid_sources[0x54]	27712	1			T1	29		T2	10		T3	7
valid_sources[0x55]	28050	1			T1	29		T2	10		T3	4
valid_sources[0x56]	26549	1			T1	24		T2	3		T3	7
valid_sources[0x57]	25342	1			T1	25		T2	5		T3	9
valid_sources[0x58]	26732	1			T1	18		T5	27		T7	1
valid_sources[0x59]	30637	1			T1	34		T2	11		T3	1
valid_sources[0x5a]	28121	1			T1	26		T2	10		T3	4
valid_sources[0x5b]	26042	1			T1	29		T2	8		T3	1
valid_sources[0x5c]	27075	1			T1	28		T2	9		T3	7
valid_sources[0x5d]	26738	1			T1	27		T2	11		T3	6
valid_sources[0x5e]	25269	1			T1	24		T2	5		T3	1
valid_sources[0x5f]	31448	1			T1	28		T2	9		T3	2
valid_sources[0x60]	25014	1			T1	22		T2	4		T3	2
valid_sources[0x61]	26214	1			T1	26		T3	5		T5	15
valid_sources[0x62]	26370	1			T1	25		T2	6		T3	2
valid_sources[0x63]	25995	1			T1	29		T2	10		T3	4
valid_sources[0x64]	27536	1			T1	26		T2	14		T3	6
valid_sources[0x65]	25706	1			T1	26		T2	12		T3	3
valid_sources[0x66]	29027	1			T1	26		T2	20		T3	4
valid_sources[0x67]	27640	1			T1	38		T2	34		T3	4
valid_sources[0x68]	26300	1			T1	29		T2	20		T3	2
valid_sources[0x69]	27549	1			T1	22		T2	6		T3	1
valid_sources[0x6a]	26872	1			T1	19		T2	17		T3	7
valid_sources[0x6b]	24648	1			T1	20		T2	11		T3	4
valid_sources[0x6c]	25268	1			T1	22		T2	17		T3	5
valid_sources[0x6d]	26210	1			T1	19		T2	8		T3	3
valid_sources[0x6e]	25628	1			T1	25		T2	5		T3	4
valid_sources[0x6f]	47590	1			T1	19		T2	8		T3	2
valid_sources[0x70]	27755	1			T1	29		T2	7		T3	3
valid_sources[0x71]	29042	1			T1	35		T3	2		T5	25
valid_sources[0x72]	27538	1			T1	36		T2	8		T3	2
valid_sources[0x73]	27260	1			T1	27		T2	1		T3	4
valid_sources[0x74]	28055	1			T1	17		T2	25		T3	8
valid_sources[0x75]	24669	1			T1	26		T2	14		T3	1
valid_sources[0x76]	31020	1			T1	29		T2	28		T3	3
valid_sources[0x77]	32473	1			T1	24		T2	14		T3	1
valid_sources[0x78]	26692	1			T1	30		T2	6		T3	4
valid_sources[0x79]	33281	1			T1	26		T2	9		T3	3
valid_sources[0x7a]	26750	1			T1	24		T2	15		T3	2
valid_sources[0x7b]	31318	1			T1	28		T2	19		T3	4
valid_sources[0x7c]	25847	1			T1	29		T2	16		T3	2
valid_sources[0x7d]	28828	1			T1	29		T2	7		T3	5
valid_sources[0x7e]	29557	1			T1	24		T2	10		T3	2
valid_sources[0x7f]	24152	1			T1	25		T2	8		T3	5
valid_sources[0x80]	26662	1			T1	27		T2	5		T3	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1046557

1

T1

558

T2

320

T3

2

values[0x0]

all_enables

biggest_size

1512677

1

T1

845

T2

408

T3

478

values[0x1]

all_enables

biggest_size

1495030

1

T1

861

T2

444

T3

406