Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3104319

1

T1

4348

T2

1808

T3

15

full_word

4055546

1

T1

2264

T2

1172

T3

886

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7159465	1			T1	6612		T2	2980		T3	901
auto[TlIntgErrCmd]	130	1			T58	5		T97	6		T98	7
auto[TlIntgErrData]	137	1			T58	4		T97	5		T98	12
auto[TlIntgErrBoth]	133	1			T58	1		T97	9		T98	11

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3852211

1

T1

4375

T2

1831

T3

13

auto[1]

3307654

1

T1

2237

T2

1149

T3

888

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	2805214	1			T1	3817		T2	1511		T3	11
auto[TlIntgErrNone]	partial	auto[1]	298731	1			T1	531		T2	297		T3	4
auto[TlIntgErrNone]	full_word	auto[0]	1046817	1			T1	558		T2	320		T3	2
auto[TlIntgErrNone]	full_word	auto[1]	3008703	1			T1	1706		T2	852		T3	884
auto[TlIntgErrCmd]	partial	auto[0]	52	1			T58	2		T97	2		T98	3
auto[TlIntgErrCmd]	partial	auto[1]	70	1			T58	3		T97	4		T98	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T98	1		T173	1		T172	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T145	2		T174	1		T175	1
auto[TlIntgErrData]	partial	auto[0]	62	1			T58	2		T97	1		T98	7
auto[TlIntgErrData]	partial	auto[1]	62	1			T58	1		T97	2		T98	5
auto[TlIntgErrData]	full_word	auto[0]	4	1			T171	1		T176	1		T173	1
auto[TlIntgErrData]	full_word	auto[1]	9	1			T58	1		T97	2		T145	2
auto[TlIntgErrBoth]	partial	auto[0]	56	1			T58	1		T97	7		T98	4
auto[TlIntgErrBoth]	partial	auto[1]	72	1			T97	2		T98	6		T145	4
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T98	1		T173	1		T177	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T145	1		T169	1		-	-