Unified Coverage Report :: Module :: prim_generic_ram_1r1w

Module : prim_generic_ram_1r1w

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1r1w

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	561264083	3287151	0	0
gen_wmask[1].MaskCheckPortA_A	561264083	3287151	0	0
gen_wmask[2].MaskCheckPortA_A	561264083	3287151	0	0
gen_wmask[3].MaskCheckPortA_A	561264083	3287151	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561264083	3287151	0	0
T1	388801	2666	0	0
T2	146164	1478	0	0
T3	3713	832	0	0
T4	765426	0	0	0
T5	367818	3136	0	0
T6	149598	832	0	0
T7	4908	0	0	0
T8	1189	0	0	0
T9	1239	0	0	0
T10	866077	7653	0	0
T11	650449	17938	0	0
T12	2680	134	0	0
T14	57502	832	0	0
T15	0	31396	0	0
T16	0	1598	0	0
T18	0	4864	0	0
T24	0	5797	0	0
T25	0	1702	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561264083	3287151	0	0
T1	388801	2666	0	0
T2	146164	1478	0	0
T3	3713	832	0	0
T4	765426	0	0	0
T5	367818	3136	0	0
T6	149598	832	0	0
T7	4908	0	0	0
T8	1189	0	0	0
T9	1239	0	0	0
T10	866077	7653	0	0
T11	650449	17938	0	0
T12	2680	134	0	0
T14	57502	832	0	0
T15	0	31396	0	0
T16	0	1598	0	0
T18	0	4864	0	0
T24	0	5797	0	0
T25	0	1702	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561264083	3287151	0	0
T1	388801	2666	0	0
T2	146164	1478	0	0
T3	3713	832	0	0
T4	765426	0	0	0
T5	367818	3136	0	0
T6	149598	832	0	0
T7	4908	0	0	0
T8	1189	0	0	0
T9	1239	0	0	0
T10	866077	7653	0	0
T11	650449	17938	0	0
T12	2680	134	0	0
T14	57502	832	0	0
T15	0	31396	0	0
T16	0	1598	0	0
T18	0	4864	0	0
T24	0	5797	0	0
T25	0	1702	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	561264083	3287151	0	0
T1	388801	2666	0	0
T2	146164	1478	0	0
T3	3713	832	0	0
T4	765426	0	0	0
T5	367818	3136	0	0
T6	149598	832	0	0
T7	4908	0	0	0
T8	1189	0	0	0
T9	1239	0	0	0
T10	866077	7653	0	0
T11	650449	17938	0	0
T12	2680	134	0	0
T14	57502	832	0	0
T15	0	31396	0	0
T16	0	1598	0	0
T18	0	4864	0	0
T24	0	5797	0	0
T25	0	1702	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			==> MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	411485887	2082210	0	0
gen_wmask[1].MaskCheckPortA_A	411485887	2082210	0	0
gen_wmask[2].MaskCheckPortA_A	411485887	2082210	0	0
gen_wmask[3].MaskCheckPortA_A	411485887	2082210	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411485887	2082210	0	0
T1	315768	952	0	0
T2	99050	481	0	0
T3	3469	832	0	0
T4	655492	0	0	0
T5	323009	3136	0	0
T6	41103	832	0	0
T7	4908	0	0	0
T8	1189	0	0	0
T9	1239	0	0	0
T10	591296	3328	0	0
T11	0	6101	0	0
T12	0	33	0	0
T14	0	832	0	0
T15	0	14207	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411485887	2082210	0	0
T1	315768	952	0	0
T2	99050	481	0	0
T3	3469	832	0	0
T4	655492	0	0	0
T5	323009	3136	0	0
T6	41103	832	0	0
T7	4908	0	0	0
T8	1189	0	0	0
T9	1239	0	0	0
T10	591296	3328	0	0
T11	0	6101	0	0
T12	0	33	0	0
T14	0	832	0	0
T15	0	14207	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411485887	2082210	0	0
T1	315768	952	0	0
T2	99050	481	0	0
T3	3469	832	0	0
T4	655492	0	0	0
T5	323009	3136	0	0
T6	41103	832	0	0
T7	4908	0	0	0
T8	1189	0	0	0
T9	1239	0	0	0
T10	591296	3328	0	0
T11	0	6101	0	0
T12	0	33	0	0
T14	0	832	0	0
T15	0	14207	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411485887	2082210	0	0
T1	315768	952	0	0
T2	99050	481	0	0
T3	3469	832	0	0
T4	655492	0	0	0
T5	323009	3136	0	0
T6	41103	832	0	0
T7	4908	0	0	0
T8	1189	0	0	0
T9	1239	0	0	0
T10	591296	3328	0	0
T11	0	6101	0	0
T12	0	33	0	0
T14	0	832	0	0
T15	0	14207	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	149778196	1204941	0	0
gen_wmask[1].MaskCheckPortA_A	149778196	1204941	0	0
gen_wmask[2].MaskCheckPortA_A	149778196	1204941	0	0
gen_wmask[3].MaskCheckPortA_A	149778196	1204941	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149778196	1204941	0	0
T1	73033	1714	0	0
T2	47114	997	0	0
T3	244	0	0	0
T4	109934	0	0	0
T5	44809	0	0	0
T6	108495	0	0	0
T10	274781	4325	0	0
T11	650449	11837	0	0
T12	2680	101	0	0
T14	57502	0	0	0
T15	0	17189	0	0
T16	0	1598	0	0
T18	0	4864	0	0
T24	0	5797	0	0
T25	0	1702	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149778196	1204941	0	0
T1	73033	1714	0	0
T2	47114	997	0	0
T3	244	0	0	0
T4	109934	0	0	0
T5	44809	0	0	0
T6	108495	0	0	0
T10	274781	4325	0	0
T11	650449	11837	0	0
T12	2680	101	0	0
T14	57502	0	0	0
T15	0	17189	0	0
T16	0	1598	0	0
T18	0	4864	0	0
T24	0	5797	0	0
T25	0	1702	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149778196	1204941	0	0
T1	73033	1714	0	0
T2	47114	997	0	0
T3	244	0	0	0
T4	109934	0	0	0
T5	44809	0	0	0
T6	108495	0	0	0
T10	274781	4325	0	0
T11	650449	11837	0	0
T12	2680	101	0	0
T14	57502	0	0	0
T15	0	17189	0	0
T16	0	1598	0	0
T18	0	4864	0	0
T24	0	5797	0	0
T25	0	1702	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149778196	1204941	0	0
T1	73033	1714	0	0
T2	47114	997	0	0
T3	244	0	0	0
T4	109934	0	0	0
T5	44809	0	0	0
T6	108495	0	0	0
T10	274781	4325	0	0
T11	650449	11837	0	0
T12	2680	101	0	0
T14	57502	0	0	0
T15	0	17189	0	0
T16	0	1598	0	0
T18	0	4864	0	0
T24	0	5797	0	0
T25	0	1702	0	0